superio/ite/common: Make PECI a thermal mode
Instead of setting "peci_tmpin" in the devicetree, THERMAL_PECI is now
a mode of TMPIN like THERMAL_RESISTOR and THERMAL_DIODE. Since the logic
to set temperature offsets and limits is in the function that sets
thermal modes, it makes sense to treat PECI as yet another mode.
As of this commit, there are no boards that actually use peci_tmpin from
ite/common. There are three boards that have a similar device tree
option, but those boards use it8772f, which implements all superio
functions on its own.
The first user will probably be Gigabyte GA-Z77-DS3H.
Change-Id: I39da50c124ad767f8681302733cf004622975e81
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/22076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c
index 932f827..44926bc 100644
--- a/src/superio/ite/common/env_ctrl.c
+++ b/src/superio/ite/common/env_ctrl.c
@@ -64,13 +64,10 @@
}
/*
- * Setup External Temperature to read via PECI into TMPINx register
+ * Setup PECI interface
*/
-static void enable_peci(const u16 base, const u8 tmpin)
+static void enable_peci(const u16 base)
{
- if (tmpin == 0 || tmpin > ITE_EC_TMPIN_CNT)
- return;
-
/* Enable PECI interface */
ite_ec_write(base, ITE_EC_INTERFACE_SELECT,
ITE_EC_INTERFACE_SEL_PECI |
@@ -88,14 +85,10 @@
ite_ec_write(base, ITE_EC_EXTEMP_CONTROL,
ITE_EC_EXTEMP_CTRL_AUTO_4HZ |
ITE_EC_EXTEMP_CTRL_AUTO_START);
-
- /* External Temperature reported in TMPINx register */
- ite_ec_write(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE,
- (tmpin & 3) << 6);
}
/*
- * Set up External Temperature to read via thermal diode/resistor
+ * Set up External Temperature to read via PECI or thermal diode/resistor
* into TMPINx register
*/
static void enable_tmpin(const u16 base, const u8 tmpin,
@@ -106,6 +99,14 @@
reg = ite_ec_read(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE);
switch (conf->mode) {
+ case THERMAL_PECI:
+ if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK) {
+ printk(BIOS_WARNING, "PECI specified for multiple TMPIN\n");
+ return;
+ }
+ enable_peci(base);
+ reg |= ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin);
+ break;
case THERMAL_DIODE:
reg |= ITE_EC_ADC_TEMP_DIODE_MODE(tmpin);
break;
@@ -242,9 +243,6 @@
fan_ctl |= ITE_EC_FAN_CTL_POLARITY_HIGH;
ite_ec_write(base, ITE_EC_FAN_CTL_MODE, fan_ctl);
- /* Enable PECI if configured */
- enable_peci(base, conf->peci_tmpin);
-
/* Enable HWM if configured */
for (i = 0; i < ITE_EC_TMPIN_CNT; ++i)
enable_tmpin(base, i + 1, &conf->tmpin[i]);
@@ -261,6 +259,7 @@
* busy state. Therefore, check the status and terminate
* processes if needed.
*/
- if (conf->peci_tmpin != 0)
- extemp_force_idle_status(base);
+ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i)
+ if (conf->tmpin[i].mode == THERMAL_PECI)
+ extemp_force_idle_status(base);
}
diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h
index 64603c6..8ce682e 100644
--- a/src/superio/ite/common/env_ctrl.h
+++ b/src/superio/ite/common/env_ctrl.h
@@ -91,6 +91,7 @@
#define ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE 0x50
#define ITE_EC_ADC_TEMP_CHANNEL_ENABLE 0x51
+#define ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK (3 << 6)
#define ITE_EC_ADC_TEMP_EXT_REPORTS_TO(x) (((x) & 3) << 6)
#define ITE_EC_ADC_TEMP_RESISTOR_MODE(x) (1 << ((x)+2))
#define ITE_EC_ADC_TEMP_DIODE_MODE(x) (1 << ((x)-1))
diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h
index a535af6..a3c6ae4 100644
--- a/src/superio/ite/common/env_ctrl_chip.h
+++ b/src/superio/ite/common/env_ctrl_chip.h
@@ -26,6 +26,7 @@
THERMAL_MODE_DISABLED = 0,
THERMAL_DIODE,
THERMAL_RESISTOR,
+ THERMAL_PECI,
};
struct ite_ec_thermal_config {
@@ -77,12 +78,6 @@
struct ite_ec_config {
/*
- * Enable external temperature sensor to use PECI GetTemp()
- * command and store in register TMPIN 1, 2, or 3.
- */
- u8 peci_tmpin;
-
- /*
* Enable reading of voltage pins VINx.
*/
enum ite_ec_voltage_pin vin_mask;