diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 451c5dd..8b9e9e2 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -55,19 +55,19 @@
 	register "PcieRpEnable[5]" = "1"
 	register "PcieRpEnable[6]" = "1"
 
-	register "PcieClkSrcUsage[0]" = "0x00"
-	register "PcieClkSrcUsage[1]" = "0x01"
-	register "PcieClkSrcUsage[2]" = "0x02"
-	register "PcieClkSrcUsage[3]" = "0xFF"
-	register "PcieClkSrcUsage[4]" = "0xFF"
-	register "PcieClkSrcUsage[5]" = "0xFF"
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
 
-	register "PcieClkSrcClkReq[0]" = "0xFF"
-	register "PcieClkSrcClkReq[1]" = "0xFF"
-	register "PcieClkSrcClkReq[2]" = "0xFF"
-	register "PcieClkSrcClkReq[3]" = "0xFF"
-	register "PcieClkSrcClkReq[4]" = "0xFF"
-	register "PcieClkSrcClkReq[5]" = "0xFF"
+	register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
 
 	# Disable all L1 substates for PCIe root ports
 	register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"