soc/amd/cezanne: Use common fsp-s preloader
Use the common preloader for fsp-s
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ibbed17445c3cd8fa4da671f2a90532d3c39ad08b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 0de2ab7..6b6bec3 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -66,6 +66,7 @@
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
select SOC_AMD_COMMON_FSP_DMI_TABLES
select SOC_AMD_COMMON_FSP_PCI
+ select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SSE2
select UDK_2017_BINDING
select USE_DDR4
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 091e63f..a028da0 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -37,7 +37,6 @@
ramstage-y += graphics.c
ramstage-y += i2c.c
ramstage-y += mca.c
-ramstage-y += preload.c
ramstage-y += reset.c
ramstage-y += root_complex.c
ramstage-y += uart.c
diff --git a/src/soc/amd/cezanne/preload.c b/src/soc/amd/cezanne/preload.c
deleted file mode 100644
index d8b0891..0000000
--- a/src/soc/amd/cezanne/preload.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootstate.h>
-#include <fsp/api.h>
-
-static void start_fsps_preload(void *unused)
-{
- preload_fsps();
-}
-
-BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL);