| commit | 168ef399c43ad79a40a8bbb2de921a2bd906b3f5 | [log] [tgz] |
|---|---|---|
| author | Elyes HAOUAS <ehaouas@noos.fr> | Tue Jun 27 22:54:42 2017 +0200 |
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | Wed Jun 28 00:23:32 2017 +0000 |
| tree | 16613245bebd7920cf3e7ce41f0d7bb5441f05e2 | |
| parent | 70083a1de9e12d8dbd3ba70e7a36a7282090f0e0 [diff] [blame] |
cpu/*: Add whitespace around '<<' Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 857873a..8038177 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -40,7 +40,7 @@ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4 post_code(0xa1)