mb/google/nissa: Add devicetree
Fill in devicetree for nissa baseboard based on schematics.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
TEST=abuild -a -x -c max -p none -t google/brya -b nereid
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index a5e2217..74b24c8 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -1,4 +1,148 @@
chip soc/intel/alderlake
+
+ # GPE configuration
+ register "pmc_gpe0_dw0" = "GPP_A"
+ register "pmc_gpe0_dw1" = "GPP_H"
+ register "pmc_gpe0_dw2" = "GPP_F"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # S0ix enable
+ register "s0ix_enable" = "1"
+
+ # Enable CNVi BT
+ register "CnviBtCore" = "true"
+
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
+
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+ register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # HD Audio
+ register "PchHdaDspEnable" = "1"
+ register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
+ register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
+ register "PchHdaIDispCodecEnable" = "1"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| I2C0 | TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | Sub-board(PSensor)/WCAM |
+ #| I2C3 | Audio |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ }"
+
device domain 0 on
+ device ref igpu on end
+ device ref dtt on end
+ device ref tcss_xhci on end
+ device ref xhci on end
+ device ref shared_sram on end
+ device ref cnvi_wifi on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end
+ device ref i2c0 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+ device i2c 50 on end
+ end
+ end
+ device ref heci1 on end
+ device ref emmc on end
+ device ref pcie_rp7 on
+ # Enable SD Card PCIE 7 using clk 3
+ register "pch_pcie_rp[PCH_RP(7)]" = "{
+ .clk_src = 3,
+ .clk_req = 3,
+ .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
+ register "srcclk_pin" = "3"
+ device generic 0 on end
+ end
+ end #PCIE7 SD card
+ device ref uart0 on end
+ device ref pch_espi on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref hda on end
end
end