commit 16246ea9ce8a5982ec3ad465f1ea12a91abbc39e
author Aaron Durbin <adurbin@chromium.org> Fri Aug 05 21:23:37 2016 -0500
committer Martin Roth <martinroth@google.com> Mon Aug 08 18:37:37 2016 +0200
tree 3d2447ce12aed51589084049e8aba5ed1fd9894d
parent 968ddf27e2a238be2aa4757700f279366fde0b2b

chromeos chipsets: select RTC usage

Since RTC is now a Kconfig ensure RTC is selected on the
x86 chipsets which are in Chrome OS devices. This allows
the eventlog to have proper timestamps instead of all
zeros.

BUG=chrome-os-partner:55993

Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/apollolake/Kconfig

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index a85d94a..a8466e1 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -41,6 +41,7 @@
 	select POSTCAR_STAGE
 	select REG_SCRIPT
 	select RELOCATABLE_RAMSTAGE	# Build fails if this is not selected
+	select RTC
 	select SMM_TSEG
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI

src/soc/intel/baytrail/Kconfig

diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index d58d4dd..b790008 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -26,6 +26,7 @@
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select REG_SCRIPT
+	select RTC
 	select SMM_TSEG
 	select SMP
 	select SPI_FLASH

src/soc/intel/braswell/Kconfig

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4dca110..c652d96 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -30,6 +30,7 @@
 	select PCIEXP_COMMON_CLOCK
 	select PLATFORM_USES_FSP1_1
 	select REG_SCRIPT
+	select RTC
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_RESET

src/soc/intel/broadwell/Kconfig

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 9be3b1d..f8ec500 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -32,6 +32,7 @@
 	select PCIEXP_COMMON_CLOCK
 	select PCIEXP_CLK_PM
 	select PCIEXP_L1_SUB_STATE
+	select RTC
 	select SMM_TSEG
 	select SMP
 	select SPI_FLASH

src/soc/intel/skylake/Kconfig

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 0ecc80d..b08c004 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -37,6 +37,7 @@
 	select REG_SCRIPT
 	select RELOCATABLE_MODULES
 	select RELOCATABLE_RAMSTAGE
+	select RTC
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_LPSS_I2C