ramstage: cache relocated ramstage in RAM
Accessing the flash part where the ramstage resides can be slow
when loading it. In order to save time in the S3 resume path a copy
of the relocated ramstage is saved just below the location the ramstage
was loaded. Then on S3 resume the cached version of the relocated
ramstage is copied back to the loaded address.
This is achieved by saving the ramstage entry point in the
romstage_handoff structure as reserving double the amount of memory
required for ramstage. This approach saves the engineering time to make
the ramstage reentrant.
The fast path in this change will only be taken when the chipset's
romstage code properly initializes the s3_resume field in the
romstage_handoff structure. If that is never set up properly then the
fast path will never be taken.
e820 entries from Linux:
BIOS-e820: [mem 0x000000007bf21000-0x000000007bfbafff] reserved
BIOS-e820: [mem 0x000000007bfbb000-0x000000007bffffff] type 16
The type 16 is the cbmem table and the reserved section contains the two
copies of the ramstage; one has been executed already and one is
the cached relocated program.
With this change the S3 resume path on the basking ridge CRB shows
to be ~200ms to hand off to the kernel:
13 entries total:
1:95,965
2:97,191 (1,225)
3:131,755 (34,564)
4:132,890 (1,135)
8:135,165 (2,274)
9:135,840 (675)
10:135,973 (132)
30:136,016 (43)
40:136,581 (564)
50:138,280 (1,699)
60:138,381 (100)
70:204,538 (66,157)
98:204,615 (77)
Change-Id: I9c7a6d173afc758eef560e09d2aef5f90a25187a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2800
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h
index c20b261..4150e8e 100644
--- a/src/include/romstage_handoff.h
+++ b/src/include/romstage_handoff.h
@@ -31,8 +31,16 @@
/* This indicates to the ramstage to reserve a chunk of memory. */
uint32_t reserve_base;
uint32_t reserve_size;
- /* Inidicate if the current boot is an S3 resume. */
+ /* Inidicate if the current boot is an S3 resume. If
+ * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is
+ * responsible for initializing this variable. Otherwise, ramstage
+ * will be re-loaded from cbfs (which can be slower since it lives
+ * in flash). */
uint32_t s3_resume;
+ /* The ramstage_entry_point is cached in the stag loading path. This
+ * cached value can only be utilized when the chipset code properly
+ * fills in the s3_resume field above. */
+ uint32_t ramstage_entry_point;
};
#if defined(__PRE_RAM__)