diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 544a93f..43f5109 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -33,14 +33,10 @@
 	int boot_mode;
 	int wake_from_s3;
 
-	if (params->bist == 0)
-		enable_lapic();
+	enable_lapic();
 
 	wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(params->bist);
-
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */