cpu/intel: Enter romstage without BIST
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 819c2e4..4b5a3b0 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -141,7 +141,6 @@
struct pei_data *pei_data;
const void *gpio_map;
const struct rcba_config_instruction *rcba_config;
- unsigned long bist;
void (*copy_spd)(struct pei_data *);
};
void romstage_common(const struct romstage_params *params);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 544a93f..43f5109 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -33,14 +33,10 @@
int boot_mode;
int wake_from_s3;
- if (params->bist == 0)
- enable_lapic();
+ enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
- /* Halt if there was a built in self test failure */
- report_bist_failure(params->bist);
-
/* Perform some early chipset initialization required
* before RAM initialization can work
*/