commit 155cf5cd2ee844e9fb86f0f2487ccca65e560f33
author Mario Scheithauer <mario.scheithauer@siemens.com> Thu Nov 10 09:34:57 2022 +0100
committer Martin L Roth <gaumless@gmail.com> Thu Nov 24 06:01:30 2022 +0000
tree d0626d306a6d84c43b8f8883a97e23febec4092f
parent 969531b6d8c015c329f96840a1337d6b7e9c5595

drivers/net/phy/m88e1512: Add interrupt enable

INTn on Marvell PHY can be routed to LED[2] pin. This setting must be
made via LED Timer Control Register on page 3.

Change-Id: Ida1efbb604c382676b9d13ac8bf14de768f93637
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69433
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/drivers/net/phy/m88e1512/m88e1512.c

diff --git a/src/drivers/net/phy/m88e1512/m88e1512.c b/src/drivers/net/phy/m88e1512/m88e1512.c
index d0883bf..a8d1c73 100644
--- a/src/drivers/net/phy/m88e1512/m88e1512.c
+++ b/src/drivers/net/phy/m88e1512/m88e1512.c
@@ -34,6 +34,22 @@
 		/* Switch back to page 0. */
 		switch_page(dev, 0);
 	}
+
+	/* INTn can be routed to LED[2] pin. */
+	if (config->enable_int) {
+		printk(BIOS_DEBUG, "%s: INTn is routed to LED[2] pin %s.\n",
+				dev_path(dev->bus->dev), dev->chip_ops->name);
+
+		/* Select page 3 to access LED function control register. */
+		switch_page(dev, 3);
+
+		reg = mdio_read(dev, LED_TIMER_CTRL_REG);
+		setbits16(&reg, LED_IRQ_ENABLE);
+		mdio_write(dev, LED_TIMER_CTRL_REG, reg);
+
+		/* Switch back to page 0. */
+		switch_page(dev, 0);
+	}
 }
 
 struct device_operations m88e1512_ops = {