src/northbridge: Capitalize CPU, RAM and ROM
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 64bf840..5296bdb 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -69,7 +69,7 @@
/* Find the limit of the remap window */
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
}
- /* Write the ram configuration registers,
+ /* Write the RAM configuration registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, 0xc4);
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 08cd023..4a3e993 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -65,7 +65,7 @@
/* Find the limit of the remap window */
remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
}
- /* Write the ram configuration registers,
+ /* Write the RAM configuration registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, TOLM);
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index b24e3a6..c987cb3 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -64,6 +64,6 @@
/* Perform system reset through CF9 interface. */
outb(0x02, 0xcf9); /* Set system reset bit. */
- outb(0x06, 0xcf9); /* Set cpu reset bit, too. */
+ outb(0x06, 0xcf9); /* Set CPU reset bit, too. */
halt();
}
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 5e59233..b15f933 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -65,7 +65,7 @@
default 0x2000
help
The amount of anticipated stack usage from the data cache
- during pre-ram rom stage execution.
+ during pre-ram ROM stage execution.
config HAVE_MRC
bool "Add a System Agent binary"
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index 10e57f4..8d37f38 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -93,7 +93,7 @@
/* Find the offset of the remap window from tolm */
remapoffsetk = remapbasek - tolmk;
}
- /* Write the ram configruation registers,
+ /* Write the RAM configruation registers,
* preserving the reserved bits.
*/
tolm_r = pci_read_config16(mc_dev, 0xc4);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index b69efbc..443716f 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -603,7 +603,7 @@
{
long dimm_mask;
- /* Test if we can read the spd and if ram is ddr or ddr2 */
+ /* Test if we can read the spd and if RAM is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
printk(BIOS_ERR, "No memory for this cpu\n");
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index aba1966..e9b1cac 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -87,7 +87,7 @@
*/
tolmk = tomk;
}
- /* Write the ram configuration registers,
+ /* Write the RAM configuration registers,
* preserving the reserved bits.
*/
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 63ee98b..4789663 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -878,7 +878,7 @@
#endif
}
-/* if ram still doesn't work do this function */
+/* if RAM still doesn't work do this function */
static void spd_set_undocumented_registers(void)
{
spd_update(0x74, 0x00000001);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 59a31de..5469059 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -85,7 +85,7 @@
static void ram_read32(u32 offset)
{
- PRINTK_DEBUG(" ram read: %08x\n", offset);
+ PRINTK_DEBUG(" RAM read: %08x\n", offset);
read32((void *)offset);
}
@@ -1453,7 +1453,7 @@
val_err:
die("Bad SPD value\n");
hw_err:
- /* If a hardware error occurs the spd rom probably does not exist.
+ /* If a hardware error occurs the spd ROM probably does not exist.
* In this case report that there is no memory
*/
sz.side1 = 0;
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 4ac7f3d..421763c 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -1121,7 +1121,7 @@
gfxstolenbase -= tsegbasedelta;
toludbase -= tsegbasedelta;
- // Test if it is possible to reclaim a hole in the ram addressing
+ // Test if it is possible to reclaim a hole in the RAM addressing
if (tom - me_uma_size > toludbase) {
// Reclaim is possible
reclaim = 1;
@@ -4080,7 +4080,7 @@
/* Set scheduler parameters */
MCHBAR32(0x4c20) = 0x10100005;
- /* Set cpu specific register */
+ /* Set CPU specific register */
set_4f8c();
/* Clear IO reset bit */