diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index ba97254..a5aa3a1 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -26,7 +26,7 @@
 #define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
 #define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
 #define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
-#define  PCI_STATUS_DEVSEL_FAST	0x000	
+#define  PCI_STATUS_DEVSEL_FAST	0x000
 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
 #define  PCI_STATUS_DEVSEL_SLOW 0x400
 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
@@ -55,8 +55,8 @@
 
 /*
  * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of 
- * 0xffffffff to the register, and reading it back.  Only 
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back.  Only
  * 1 bits are decoded.
  */
 #define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
@@ -80,7 +80,7 @@
 /* Header type 0 (normal devices) */
 #define PCI_CARDBUS_CIS		0x28
 #define PCI_SUBSYSTEM_VENDOR_ID	0x2c
-#define PCI_SUBSYSTEM_ID	0x2e  
+#define PCI_SUBSYSTEM_ID	0x2e
 #define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
 #define  PCI_ROM_ADDRESS_ENABLE	0x01
 #define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
@@ -189,7 +189,7 @@
 
 /* Hypertransport Registers */
 #define PCI_HT_CAP_SIZEOF	   4
-#define PCI_HT_CAP_HOST_CTRL       4	/* Host link control */ 
+#define PCI_HT_CAP_HOST_CTRL       4	/* Host link control */
 #define PCI_HT_CAP_HOST_WIDTH	   6	/* width value & capability  */
 #define PCI_HT_CAP_HOST_FREQ	   0x09	/* Host frequency */
 #define PCI_HT_CAP_HOST_FREQ_CAP   0x0a	/* Host Frequency capability  */