mb/intel/archercity_crb: call soc soc_config_iio to configure IIO UPD
TESTED=On Intel AC, after seleting DISPLAY_UPD_IIO_DATA to compare
IIO UPD data are expected. lspci -vvv result is also normal.
Change-Id: Icfc2a22cb2e1f95be6bfc1d712e620e19a23ce27
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
diff --git a/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h b/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h
index 2dcf6c9..3a07cb9 100644
--- a/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h
+++ b/src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h
@@ -4,6 +4,7 @@
#define _SPRSP_AC_IIO_H_
#include <defs_iio.h>
+#include <soc/soc_util.h>
/* For now only set 3 fields and hard-coded others, should be extended in the future */
#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \
@@ -38,7 +39,8 @@
/*
* Standard ArcherCity IIO PCIe Port Table
*/
-static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt0[] = {
+static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = {
+ {
/* DMI port: array index 0 */
CFG_UPD_PCIE_PORT(0, 0, 0),
/* IOU0 (PE0): array index 1 ~ 8 */
@@ -86,10 +88,8 @@
CFG_UPD_PCIE_PORT(1, 0, 0),
CFG_UPD_PCIE_PORT(0, 1, 39), /* 59:07.0 */
CFG_UPD_PCIE_PORT(1, 0, 0),
- /* ArcherCity doesn't use IOU5 ~ IOU6. */
-};
-
-static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ac_iio_pci_port_skt1[] = {
+ },
+ {
/* DMI port: array index 0 */
CFG_UPD_PCIE_PORT(1, 0, 0),
/* IOU0 (PE0): array index 1 ~ 8 */
@@ -137,6 +137,23 @@
CFG_UPD_PCIE_PORT(1, 0, 0),
CFG_UPD_PCIE_PORT(0, 1, 39), /* d7:07.0 */
CFG_UPD_PCIE_PORT(1, 0, 0),
- /* ArcherCity doesn't use IOU5 ~ IOU6. */
+ },
};
-#endif /* _SPRSP_CL_IIO_H_ */
+
+static const UINT8 ac_iio_bifur[CONFIG_MAX_SOCKET][5] = {
+ {
+ IIO_BIFURCATE_xxxxxx16,
+ IIO_BIFURCATE_xxxxxx16,
+ IIO_BIFURCATE_xxxxxx16,
+ IIO_BIFURCATE_x4x4x4x4,
+ IIO_BIFURCATE_x4x4x4x4,
+ },
+ {
+ IIO_BIFURCATE_xxxxxx16,
+ IIO_BIFURCATE_xxxxxx16,
+ IIO_BIFURCATE_xxxxxx16,
+ IIO_BIFURCATE_x4x4x4x4,
+ IIO_BIFURCATE_x4x4x4x4,
+ },
+};
+#endif /* _SPRSP_AC_IIO_H_ */
diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c
index 582fa50..6e4bd8e 100644
--- a/src/mainboard/intel/archercity_crb/romstage.c
+++ b/src/mainboard/intel/archercity_crb/romstage.c
@@ -16,59 +16,6 @@
static void mainboard_config_iio(FSPM_UPD *mupd)
{
- int port;
-
- UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
- (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
-
- /* Socket0: Array ac_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
- for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt0); port++) {
- PciePortConfig[0].SLOTIMP[port] = ac_iio_pci_port_skt0[port].SLOTIMP;
- PciePortConfig[0].SLOTPSP[port] = ac_iio_pci_port_skt0[port].SLOTPSP;
- PciePortConfig[0].PciePortEnable[port] = ac_iio_pci_port_skt0[port].PciePortEnable;
- PciePortConfig[0].PEXPHIDE[port] = ac_iio_pci_port_skt0[port].PEXPHIDE;
- PciePortConfig[0].PcieMaxPayload[port] = ac_iio_pci_port_skt0[port].PcieMaxPayload;
- PciePortConfig[0].PciePortLinkSpeed[port] = ac_iio_pci_port_skt0[port].PciePortLinkSpeed;
- PciePortConfig[0].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt0[port].DfxDnTxPresetGen3;
- }
- /* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
- for (port = ARRAY_SIZE(ac_iio_pci_port_skt0); port < MAX_IIO_PORTS_PER_SOCKET; port++) {
- PciePortConfig[0].PEXPHIDE[port] = 1;
- PciePortConfig[0].HidePEXPMenu[port] = 1;
- }
- PciePortConfig[0].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16;
- PciePortConfig[0].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16;
- PciePortConfig[0].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16;
- PciePortConfig[0].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4;
- PciePortConfig[0].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4;
-
- PciePortConfig[0].PcieGlobalAspm = 0x1;
- PciePortConfig[0].PcieMaxReadRequestSize = 0x5;
-
- /* Socket1: Array ac_iio_pci_port_skt1 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
- for (port = 0; port < ARRAY_SIZE(ac_iio_pci_port_skt1); port++) {
- PciePortConfig[1].SLOTIMP[port] = ac_iio_pci_port_skt1[port].SLOTIMP;
- PciePortConfig[1].SLOTPSP[port] = ac_iio_pci_port_skt1[port].SLOTPSP;
- PciePortConfig[1].PciePortEnable[port] = ac_iio_pci_port_skt1[port].PciePortEnable;
- PciePortConfig[1].PEXPHIDE[port] = ac_iio_pci_port_skt1[port].PEXPHIDE;
- PciePortConfig[1].PcieMaxPayload[port] = ac_iio_pci_port_skt1[port].PcieMaxPayload;
- PciePortConfig[1].PciePortLinkSpeed[port] = ac_iio_pci_port_skt1[port].PciePortLinkSpeed;
- PciePortConfig[1].DfxDnTxPresetGen3[port] = ac_iio_pci_port_skt1[port].DfxDnTxPresetGen3;
- }
- /* Socket1: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
- for (port = ARRAY_SIZE(ac_iio_pci_port_skt1); port < MAX_IIO_PORTS_PER_SOCKET; port++) {
- PciePortConfig[1].PEXPHIDE[port] = 1;
- PciePortConfig[1].HidePEXPMenu[port] = 1;
- }
- PciePortConfig[1].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16;
- PciePortConfig[1].ConfigIOU[1] = IIO_BIFURCATE_xxxxxx16;
- PciePortConfig[1].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16;
- PciePortConfig[1].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4;
- PciePortConfig[1].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4;
-
- PciePortConfig[1].PcieGlobalAspm = 0x1;
- PciePortConfig[1].PcieMaxReadRequestSize = 0x5;
-
/* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */
if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) {
printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE);
@@ -117,6 +64,6 @@
/* Set Promote Warnings to disable.
Determines if warnings are promoted to system level. */
mupd->FspmConfig.promoteWarnings = 0x0;
-
+ soc_config_iio(mupd, ac_iio_pci_port, ac_iio_bifur);
mainboard_config_iio(mupd);
}