drivers/uart: Enable override for input clock divider
Allow the platform to override the input clock divider by adding the
uart_input_clock_divider routine. This routine combines the baud-rate
oversample divider with any other input clock divider. The default
routine returns 16 which is the standard baud-rate oversampling value.
A platform may override this default "weak" routine by providing a new
routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works
around ROMCC not supporting weak routines.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Testing is successful when CorebootPayloadPkg is able to properly
initialize the serial port without using built-in values.
Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14611
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index 2f2bd2d..4b87756 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -117,7 +117,8 @@
return;
unsigned int div;
- div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16);
+ div = uart_baudrate_divisor(default_baudrate(),
+ uart_platform_refclk(), uart_input_clock_divider());
uart8250_mem_init(base, div);
}