tree c588b8d018f8dcccab02fd3b5ed85a297b997f42
parent 6b4a1ab82a49c9288f7964b9c1836729dcc340a6
author Werner Zeh <werner.zeh@siemens.com> 1667803851 +0100
committer Felix Held <felix-coreboot@felixheld.de> 1668003555 +0000

soc/intel/elkhartlake: Correct I2C base clock to 100 MHz

According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).

This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.

Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>