soc/intel/skylake: Add integrated LAN config parameters
Add parameters to configure the integrated LAN via FSP. Since
this takes over a PCI CLKREQ# pin it needs to know which pin
it should use, and there are additional parameters for LTR and
a "K1 power save" feature.
This was tested on a KBL-R board with integrated LAN, verifying
that the device is functional under Linux with the e1000e driver.
Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22856
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index a7804af..8540e21 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -135,6 +135,10 @@
/* Lan */
u8 EnableLan;
+ u8 EnableLanLtr;
+ u8 EnableLanK1Off;
+ u8 LanClkReqSupported;
+ u8 LanClkReqNumber;
/* SATA related */
u8 EnableSata;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 2df013f..96c3b60 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -186,6 +186,12 @@
params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
params->PchLanEnable = config->EnableLan;
+ if (config->EnableLan) {
+ params->PchLanLtrEnable = config->EnableLanLtr;
+ params->PchLanK1OffEnable = config->EnableLanK1Off;
+ params->PchLanClkReqSupported = config->LanClkReqSupported;
+ params->PchLanClkReqNumber = config->LanClkReqNumber;
+ }
params->SataSalpSupport = config->SataSalpSupport;
params->SsicPortEnable = config->SsicPortEnable;
params->ScsEmmcEnabled = config->ScsEmmcEnabled;