tpm: Allow separate handling of Google Ti50 TPM
A new iteration of Google's TPM implementation will advertize a new
DID:VID, but otherwise follow the same protocol as the earlier design.
This change makes use of Kconfigs TPM_GOOGLE_CR50 and TPM_GOOGLE_TI50
to be able to take slightly different code paths, when e.g. evaluating
whether TPM firmware is new enough to support certain features.
Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 1a3cb55..5263323 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1,7 +1,6 @@
config BOARD_GOOGLE_BRYA_COMMON
def_bool n
select BOARD_ROMSIZE_KB_32768
- select CR50_USE_LONG_INTERRUPT_PULSES
select DRIVERS_GENERIC_ALC1015
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_GENERIC_MAX98357A
@@ -37,7 +36,6 @@
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE
- select TPM_GOOGLE_CR50
config BOARD_GOOGLE_BASEBOARD_BRYA
def_bool n
@@ -46,6 +44,7 @@
select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
select SOC_INTEL_ALDERLAKE_PCH_P
select SYSTEM_TYPE_LAPTOP
+ select TPM_GOOGLE_CR50
config BOARD_GOOGLE_BASEBOARD_BRASK
def_bool n
@@ -57,16 +56,17 @@
select RT8168_GET_MAC_FROM_VPD
select RT8168_SET_LED_MODE
select SOC_INTEL_ALDERLAKE_PCH_P
+ select TPM_GOOGLE_CR50
config BOARD_GOOGLE_BASEBOARD_NISSA
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
- select MAINBOARD_NEEDS_I2C_TI50_WORKAROUND
select MEMORY_SOLDERDOWN
select SOC_INTEL_ALDERLAKE_PCH_N
select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
select SYSTEM_TYPE_LAPTOP
+ select TPM_GOOGLE_TI50
if BOARD_GOOGLE_BRYA_COMMON