soc/intel/jasperlake: Add PsysPmax config
Enable PSYS capability. PSYS is required to safeguard the system
stability if no charger IC.
BUG=b:281479111
TEST=emerge-dedede coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: Ibe54acaf80700252558b82f194b9536b6117b84e
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75196
Reviewed-by: Reka Norman <rekanorman@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 3e47e00..e6b8f680 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -419,6 +419,9 @@
CD_CLOCK_556_8_MHZ = 7,
} cd_clock;
+ /* Platform Power Pmax */
+ uint16_t PsysPmax;
+
/*
* This is a workaround to mitigate higher SoC power consumption in S0ix
* when the CNVI has background activity.
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 09be260..1e6731d 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -188,6 +188,13 @@
config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
config->PchPmPwrCycDur);
+ /* Set PsysPmax */
+ if (config->PsysPmax) {
+ printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax);
+ /* PsysPmax is in unit of 1/8 Watt */
+ params->PsysPmax = config->PsysPmax * 8;
+ }
+
/*
* Fill Acoustic noise mitigation related configuration
* JSL only has single VR domain (VCCIN VR), thus filling only index 0 for