commit 13f66507afdcde5170546e5ca1ce5a945895eb10
author Kyösti Mälkki <kyosti.malkki@gmail.com> Sun Mar 03 08:01:05 2019 +0200
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Mon Mar 04 15:57:39 2019 +0000
tree 40c1d05a05b05b596f290c186aa59a8b4d9768ab
parent 065857ee7fd61b05025d7a803e82f2b9b53cbc9a

device/mmio.h: Add include file for MMIO ops

MMIO operations are arch-agnostic so the include
path should not be arch/.

Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/acpi.c

diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 92a4711..127d9c8 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -17,7 +17,7 @@
 
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
-#include <arch/io.h>
+#include <device/mmio.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
 #include <chip.h>

src/soc/intel/cannonlake/bootblock/pch.c

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 5ca19e5..018ccfc 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -15,6 +15,7 @@
  */
 
 #include <console/console.h>
+#include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <intelblocks/fast_spi.h>

src/soc/intel/cannonlake/finalize.c

diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 03ff616..bc4ae02 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/mmio.h>
 #include <bootstate.h>
 #include <chip.h>
 #include <console/console.h>

src/soc/intel/cannonlake/lockdown.c

diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c
index c57cde8..e2fcc3a 100644
--- a/src/soc/intel/cannonlake/lockdown.c
+++ b/src/soc/intel/cannonlake/lockdown.c
@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <device/mmio.h>
 #include <intelblocks/chip.h>
 #include <intelpch/lockdown.h>
 #include <soc/pm.h>

src/soc/intel/cannonlake/pmc.c

diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index 84bfba0..931c4af 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -18,6 +18,7 @@
 #include <bootstate.h>
 #include <chip.h>
 #include <console/console.h>
+#include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include <intelblocks/pmc.h>

src/soc/intel/cannonlake/pmutil.c

diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 6783b93..7d6ee65 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -21,7 +21,7 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <arch/io.h>
+#include <device/mmio.h>
 #include <cbmem.h>
 #include <device/device.h>
 #include <device/pci.h>

src/soc/intel/cannonlake/romstage/power_state.c

diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c
index 4214fcc..9137507 100644
--- a/src/soc/intel/cannonlake/romstage/power_state.c
+++ b/src/soc/intel/cannonlake/romstage/power_state.c
@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
+#include <device/mmio.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <intelblocks/pmclib.h>