tree 223ee5c1d60aba6ab36628d5154c01f68318b58b
parent 2873cc68043adecefd4640718f6b94dad0f0ae3f
author Ivy Jian <ivy.jian@quanta.corp-partner.google.com> 1701155860 +0800
committer Shelley Chen <shchen@google.com> 1701389547 +0000

mb/google/brox: Update storage settings for SSD and UFS

Brox has SSD and UFS storage per different SKU.
1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio
settings according to the schematic.
2. Enable UFS, also enable ISH since it is PCI function 0, required
for UFS function 7 to be enabled.
3. Set unused SRCCLKREQ signals to NC.
4. Remove unused gpio settings in variant gpio table to prevent
unexpected overrides.

BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>