This does the following:
cd coreboot/src/southbridge
svn mv i82801ca i82801cx
svn mv i82801dbm i82801dx
svn mv i82801er i82801ex
svn copy i82801xx i82801bx
svn mv i82801xx i82801ax
Plus, fixing up the filenames in these directories and the romstage.c and
Kconfig files of the mainboards using those drivers.
Plus, switching the thomson ip1000 and rca rm4100 to the i82801dx driver.
There's a lot more to be done, like
- adding device IDs for the ICH3 and newer drivers that have been kept in
i82801xx so far
- drop the additional parts support from the ax and bx drivers.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig
index 92be286..61cd796 100644
--- a/src/southbridge/intel/Kconfig
+++ b/src/southbridge/intel/Kconfig
@@ -1,10 +1,11 @@
source src/southbridge/intel/esb6300/Kconfig
source src/southbridge/intel/i3100/Kconfig
source src/southbridge/intel/i82371eb/Kconfig
-source src/southbridge/intel/i82801ca/Kconfig
-source src/southbridge/intel/i82801dbm/Kconfig
-source src/southbridge/intel/i82801er/Kconfig
+source src/southbridge/intel/i82801ax/Kconfig
+source src/southbridge/intel/i82801bx/Kconfig
+source src/southbridge/intel/i82801cx/Kconfig
+source src/southbridge/intel/i82801dx/Kconfig
+source src/southbridge/intel/i82801ex/Kconfig
source src/southbridge/intel/i82801gx/Kconfig
-source src/southbridge/intel/i82801xx/Kconfig
source src/southbridge/intel/i82870/Kconfig
source src/southbridge/intel/pxhd/Kconfig
diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc
index e53450f..12ba710 100644
--- a/src/southbridge/intel/Makefile.inc
+++ b/src/southbridge/intel/Makefile.inc
@@ -1,11 +1,12 @@
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_ESB6300) += esb6300
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I3100) += i3100
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CA) += i82801ca
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DBM) += i82801dbm
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801ER) += i82801er
+subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax
+subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx
+subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx
+subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx
+subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870
subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd
diff --git a/src/southbridge/intel/i82801xx/Kconfig b/src/southbridge/intel/i82801ax/Kconfig
similarity index 95%
rename from src/southbridge/intel/i82801xx/Kconfig
rename to src/southbridge/intel/i82801ax/Kconfig
index f86c65f..25e2c3aa 100644
--- a/src/southbridge/intel/i82801xx/Kconfig
+++ b/src/southbridge/intel/i82801ax/Kconfig
@@ -18,6 +18,6 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-config SOUTHBRIDGE_INTEL_I82801XX
+config SOUTHBRIDGE_INTEL_I82801AX
bool
diff --git a/src/southbridge/intel/i82801xx/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc
similarity index 69%
rename from src/southbridge/intel/i82801xx/Makefile.inc
rename to src/southbridge/intel/i82801ax/Makefile.inc
index 875141f..3e66f04 100644
--- a/src/southbridge/intel/i82801xx/Makefile.inc
+++ b/src/southbridge/intel/i82801ax/Makefile.inc
@@ -18,21 +18,21 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-driver-y += i82801xx.o
-driver-y += i82801xx_ac97.o
-driver-y += i82801xx_ide.o
-driver-y += i82801xx_lpc.o
-driver-y += i82801xx_nic.o
-driver-y += i82801xx_pci.o
-driver-y += i82801xx_sata.o
-# driver-y += i82801xx_smbus.o
-driver-y += i82801xx_usb.o
-driver-y += i82801xx_usb_ehci.o
+driver-y += i82801ax.o
+driver-y += i82801ax_ac97.o
+driver-y += i82801ax_ide.o
+driver-y += i82801ax_lpc.o
+driver-y += i82801ax_nic.o
+driver-y += i82801ax_pci.o
+driver-y += i82801ax_sata.o
+# driver-y += i82801ax_smbus.o
+driver-y += i82801ax_usb.o
+driver-y += i82801ax_usb_ehci.o
-obj-y += i82801xx_reset.o
-obj-y += i82801xx_watchdog.o
+obj-y += i82801ax_reset.o
+obj-y += i82801ax_watchdog.o
# TODO: What about cmos_failover.c?
-# TODO: Fix and enable i82801xx_smbus.o later.
+# TODO: Fix and enable i82801ax_smbus.o later.
diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801ax/chip.h
similarity index 85%
rename from src/southbridge/intel/i82801xx/chip.h
rename to src/southbridge/intel/i82801ax/chip.h
index 443df451..90bbfcb 100644
--- a/src/southbridge/intel/i82801xx/chip.h
+++ b/src/southbridge/intel/i82801ax/chip.h
@@ -19,7 +19,7 @@
*/
/*
- * The i82801xx code currently supports:
+ * The i82801ax code currently supports:
* - 82801AA
* - 82801AB
* - 82801BA
@@ -32,10 +32,10 @@
* This code should NOT be used for ICH6 and later versions.
*/
-#ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
-#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
+#ifndef SOUTHBRIDGE_INTEL_I82801AX_CHIP_H
+#define SOUTHBRIDGE_INTEL_I82801AX_CHIP_H
-struct southbridge_intel_i82801xx_config {
+struct southbridge_intel_i82801ax_config {
/**
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
@@ -53,6 +53,6 @@
uint8_t ide1_enable;
};
-extern struct chip_operations southbridge_intel_i82801xx_ops;
+extern struct chip_operations southbridge_intel_i82801ax_ops;
#endif
diff --git a/src/southbridge/intel/i82801xx/cmos_failover.c b/src/southbridge/intel/i82801ax/cmos_failover.c
similarity index 97%
rename from src/southbridge/intel/i82801xx/cmos_failover.c
rename to src/southbridge/intel/i82801ax/cmos_failover.c
index 9307f40..a770005 100644
--- a/src/southbridge/intel/i82801xx/cmos_failover.c
+++ b/src/southbridge/intel/i82801ax/cmos_failover.c
@@ -16,7 +16,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include "i82801xx.h"
+#include "i82801ax.h"
static void check_cmos_failed(void)
{
diff --git a/src/southbridge/intel/i82801xx/i82801xx.c b/src/southbridge/intel/i82801ax/i82801ax.c
similarity index 90%
rename from src/southbridge/intel/i82801xx/i82801xx.c
rename to src/southbridge/intel/i82801ax/i82801ax.c
index 385b122..ea4cda6 100644
--- a/src/southbridge/intel/i82801xx/i82801xx.c
+++ b/src/southbridge/intel/i82801ax/i82801ax.c
@@ -23,9 +23,9 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include "i82801xx.h"
+#include "i82801ax.h"
-void i82801xx_enable(device_t dev)
+void i82801ax_enable(device_t dev)
{
unsigned int index = 0;
uint16_t cur_disable_mask, new_disable_mask;
@@ -61,7 +61,7 @@
}
}
-struct chip_operations southbridge_intel_i82801xx_ops = {
- CHIP_NAME("Intel 82801 Series Southbridge")
- .enable_dev = i82801xx_enable,
+struct chip_operations southbridge_intel_i82801ax_ops = {
+ CHIP_NAME("Intel ICH/ICH0 (82801AA/AB) Series Southbridge")
+ .enable_dev = i82801ax_enable,
};
diff --git a/src/southbridge/intel/i82801xx/i82801xx.h b/src/southbridge/intel/i82801ax/i82801ax.h
similarity index 94%
rename from src/southbridge/intel/i82801xx/i82801xx.h
rename to src/southbridge/intel/i82801ax/i82801ax.h
index d90cc32..f9b4977 100644
--- a/src/southbridge/intel/i82801xx/i82801xx.h
+++ b/src/southbridge/intel/i82801ax/i82801ax.h
@@ -18,12 +18,12 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
-#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
+#ifndef SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H
+#define SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
-extern void i82801xx_enable(device_t dev);
+extern void i82801ax_enable(device_t dev);
#endif
#define PCI_DMA_CFG 0x90
@@ -117,4 +117,4 @@
/* HPET, if present */
#define HPET_ADDR 0xfed0000
-#endif /* SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H */
+#endif /* SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_ac97.c b/src/southbridge/intel/i82801ax/i82801ax_ac97.c
similarity index 98%
rename from src/southbridge/intel/i82801xx/i82801xx_ac97.c
rename to src/southbridge/intel/i82801ax/i82801ax_ac97.c
index ace04ff..7ef4142 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_ac97.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_ac97.c
@@ -25,7 +25,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801ax.h"
static struct device_operations ac97_ops = {
.read_resources = pci_dev_read_resources,
@@ -33,7 +33,7 @@
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801ax_enable,
};
/* 82801AA (ICH) */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c
similarity index 96%
rename from src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
rename to src/southbridge/intel/i82801ax/i82801ax_early_lpc.c
index 3ae91d7..abcf9c6 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c
@@ -18,7 +18,7 @@
*
*/
-static void i82801xx_halt_tco_timer(void)
+static void i82801ax_halt_tco_timer(void)
{
device_t dev;
uint16_t halt_tco_timer;
diff --git a/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
similarity index 97%
copy from src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
copy to src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
index d1bd051..d80c29c 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c
@@ -21,8 +21,8 @@
*/
#include <device/pci_ids.h>
-#include "i82801xx.h"
-#include "i82801xx_smbus.h"
+#include "i82801ax.h"
+#include "i82801ax_smbus.h"
static void enable_smbus(void)
{
diff --git a/src/southbridge/intel/i82801xx/i82801xx_ide.c b/src/southbridge/intel/i82801ax/i82801ax_ide.c
similarity index 96%
rename from src/southbridge/intel/i82801xx/i82801xx_ide.c
rename to src/southbridge/intel/i82801ax/i82801ax_ide.c
index 4173cc6..c13fb4d 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_ide.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_ide.c
@@ -25,9 +25,9 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801ax.h"
-typedef struct southbridge_intel_i82801xx_config config_t;
+typedef struct southbridge_intel_i82801ax_config config_t;
static void ide_init(struct device *dev)
{
@@ -67,7 +67,7 @@
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801ax_enable,
};
/* 82801AA */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
similarity index 91%
copy from src/southbridge/intel/i82801xx/i82801xx_lpc.c
copy to src/southbridge/intel/i82801ax/i82801ax_lpc.c
index f7fae37..590f057 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_lpc.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
@@ -30,13 +30,13 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
-#include "i82801xx.h"
+#include "i82801ax.h"
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
#define NMI_OFF 0
-typedef struct southbridge_intel_i82801xx_config config_t;
+typedef struct southbridge_intel_i82801ax_config config_t;
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@@ -74,7 +74,7 @@
* specific IRQ values in your mainboards Config.lb.
*/
-void i82801xx_enable_apic(struct device *dev)
+void i82801ax_enable_apic(struct device *dev)
{
uint32_t reg32;
volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
@@ -108,7 +108,7 @@
*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
}
-void i82801xx_enable_serial_irqs(struct device *dev)
+void i82801ax_enable_serial_irqs(struct device *dev)
{
/* Set packet length and toggle silent mode bit. */
pci_write_config8(dev, SERIRQ_CNTL,
@@ -118,7 +118,7 @@
/* TODO: Explain/#define the real meaning of these magic numbers. */
}
-static void i82801xx_pirq_init(device_t dev, uint16_t ich_model)
+static void i82801ax_pirq_init(device_t dev, uint16_t ich_model)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -176,7 +176,7 @@
}
}
-static void i82801xx_power_options(device_t dev)
+static void i82801ax_power_options(device_t dev)
{
uint8_t byte;
int pwr_on = -1;
@@ -220,7 +220,7 @@
}
}
-void i82801xx_rtc_init(struct device *dev)
+void i82801ax_rtc_init(struct device *dev)
{
uint8_t reg8;
uint32_t reg32;
@@ -240,7 +240,7 @@
pci_write_config8(dev, RTC_CONF, 0x04);
}
-void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask)
+void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
{
uint16_t reg16;
int i;
@@ -255,7 +255,7 @@
pci_write_config16(dev, PCI_DMA_CFG, reg16);
}
-static void i82801xx_lpc_decode_en(device_t dev, uint16_t ich_model)
+static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model)
{
/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
@@ -302,36 +302,36 @@
pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
- i82801xx_enable_apic(dev);
+ i82801ax_enable_apic(dev);
- i82801xx_enable_serial_irqs(dev);
+ i82801ax_enable_serial_irqs(dev);
/* Setup the PIRQ. */
- i82801xx_pirq_init(dev, ich_model);
+ i82801ax_pirq_init(dev, ich_model);
/* Setup power options. */
- i82801xx_power_options(dev);
+ i82801ax_power_options(dev);
/* Set the state of the GPIO lines. */
gpio_init(dev, ich_model);
/* Initialize the real time clock. */
- i82801xx_rtc_init(dev);
+ i82801ax_rtc_init(dev);
/* Route DMA. */
- i82801xx_lpc_route_dma(dev, 0xff);
+ i82801ax_lpc_route_dma(dev, 0xff);
/* Initialize ISA DMA. */
isa_dma_init();
/* Setup decode ports and LPC I/F enables. */
- i82801xx_lpc_decode_en(dev, ich_model);
+ i82801ax_lpc_decode_en(dev, ich_model);
/* Initialize the High Precision Event Timers, if present. */
enable_hpet(dev);
}
-static void i82801xx_lpc_read_resources(device_t dev)
+static void i82801ax_lpc_read_resources(device_t dev)
{
struct resource *res;
@@ -357,19 +357,19 @@
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void i82801xx_lpc_enable_resources(device_t dev)
+static void i82801ax_lpc_enable_resources(device_t dev)
{
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static struct device_operations lpc_ops = {
- .read_resources = i82801xx_lpc_read_resources,
+ .read_resources = i82801ax_lpc_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = i82801xx_lpc_enable_resources,
+ .enable_resources = i82801ax_lpc_enable_resources,
.init = lpc_init,
.scan_bus = scan_static_bus,
- .enable = i82801xx_enable,
+ .enable = i82801ax_enable,
};
static const struct pci_driver i82801aa_lpc __pci_driver = {
diff --git a/src/southbridge/intel/i82801xx/i82801xx_nic.c b/src/southbridge/intel/i82801ax/i82801ax_nic.c
similarity index 100%
rename from src/southbridge/intel/i82801xx/i82801xx_nic.c
rename to src/southbridge/intel/i82801ax/i82801ax_nic.c
diff --git a/src/southbridge/intel/i82801xx/i82801xx_pci.c b/src/southbridge/intel/i82801ax/i82801ax_pci.c
similarity index 100%
rename from src/southbridge/intel/i82801xx/i82801xx_pci.c
rename to src/southbridge/intel/i82801ax/i82801ax_pci.c
diff --git a/src/southbridge/intel/i82801xx/i82801xx_reset.c b/src/southbridge/intel/i82801ax/i82801ax_reset.c
similarity index 100%
rename from src/southbridge/intel/i82801xx/i82801xx_reset.c
rename to src/southbridge/intel/i82801ax/i82801ax_reset.c
diff --git a/src/southbridge/intel/i82801xx/i82801xx_sata.c b/src/southbridge/intel/i82801ax/i82801ax_sata.c
similarity index 97%
copy from src/southbridge/intel/i82801xx/i82801xx_sata.c
copy to src/southbridge/intel/i82801ax/i82801ax_sata.c
index de8b3b0..5d6d6f2 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_sata.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_sata.c
@@ -23,7 +23,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801ax.h"
/* TODO: Set dynamically, if the user only wants one SATA channel or none
* at all.
@@ -64,7 +64,7 @@
.enable_resources = pci_dev_enable_resources,
.init = sata_init,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801ax_enable,
};
/* 82801EB */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_smbus.c b/src/southbridge/intel/i82801ax/i82801ax_smbus.c
similarity index 98%
copy from src/southbridge/intel/i82801xx/i82801xx_smbus.c
copy to src/southbridge/intel/i82801ax/i82801ax_smbus.c
index 1608650..739cfdb 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_smbus.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_smbus.c
@@ -24,7 +24,7 @@
#include <smbus.h>
#include <pci.h>
#include <arch/io.h>
-#include "i82801xx.h"
+#include "i82801ax.h"
#include "i82801_smbus.h"
static int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
diff --git a/src/southbridge/intel/i82801xx/i82801xx_smbus.h b/src/southbridge/intel/i82801ax/i82801ax_smbus.h
similarity index 100%
rename from src/southbridge/intel/i82801xx/i82801xx_smbus.h
rename to src/southbridge/intel/i82801ax/i82801ax_smbus.h
diff --git a/src/southbridge/intel/i82801xx/i82801xx_usb.c b/src/southbridge/intel/i82801ax/i82801ax_usb.c
similarity index 98%
rename from src/southbridge/intel/i82801xx/i82801xx_usb.c
rename to src/southbridge/intel/i82801ax/i82801ax_usb.c
index 74bbbee..a1d36e8 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_usb.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_usb.c
@@ -24,7 +24,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801ax.h"
static void usb_init(struct device *dev)
{
@@ -37,7 +37,7 @@
.enable_resources = pci_dev_enable_resources,
.init = usb_init,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801ax_enable,
};
/* 82801AA (ICH) */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c b/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c
similarity index 97%
copy from src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
copy to src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c
index 032f198..a3f7e7c 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801ax.h"
static void usb_ehci_init(struct device *dev)
{
@@ -65,7 +65,7 @@
.enable_resources = pci_dev_enable_resources,
.init = usb_ehci_init,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801ax_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/intel/i82801xx/i82801xx_watchdog.c b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c
similarity index 100%
rename from src/southbridge/intel/i82801xx/i82801xx_watchdog.c
rename to src/southbridge/intel/i82801ax/i82801ax_watchdog.c
diff --git a/src/southbridge/intel/i82801xx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig
similarity index 95%
copy from src/southbridge/intel/i82801xx/Kconfig
copy to src/southbridge/intel/i82801bx/Kconfig
index f86c65f..682b725 100644
--- a/src/southbridge/intel/i82801xx/Kconfig
+++ b/src/southbridge/intel/i82801bx/Kconfig
@@ -18,6 +18,6 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-config SOUTHBRIDGE_INTEL_I82801XX
+config SOUTHBRIDGE_INTEL_I82801BX
bool
diff --git a/src/southbridge/intel/i82801xx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc
similarity index 69%
copy from src/southbridge/intel/i82801xx/Makefile.inc
copy to src/southbridge/intel/i82801bx/Makefile.inc
index 875141f..3d7d618 100644
--- a/src/southbridge/intel/i82801xx/Makefile.inc
+++ b/src/southbridge/intel/i82801bx/Makefile.inc
@@ -18,21 +18,21 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-driver-y += i82801xx.o
-driver-y += i82801xx_ac97.o
-driver-y += i82801xx_ide.o
-driver-y += i82801xx_lpc.o
-driver-y += i82801xx_nic.o
-driver-y += i82801xx_pci.o
-driver-y += i82801xx_sata.o
-# driver-y += i82801xx_smbus.o
-driver-y += i82801xx_usb.o
-driver-y += i82801xx_usb_ehci.o
+driver-y += i82801bx.o
+driver-y += i82801bx_ac97.o
+driver-y += i82801bx_ide.o
+driver-y += i82801bx_lpc.o
+driver-y += i82801bx_nic.o
+driver-y += i82801bx_pci.o
+driver-y += i82801bx_sata.o
+# driver-y += i82801bx_smbus.o
+driver-y += i82801bx_usb.o
+driver-y += i82801bx_usb_ehci.o
-obj-y += i82801xx_reset.o
-obj-y += i82801xx_watchdog.o
+obj-y += i82801bx_reset.o
+obj-y += i82801bx_watchdog.o
# TODO: What about cmos_failover.c?
-# TODO: Fix and enable i82801xx_smbus.o later.
+# TODO: Fix and enable i82801bx_smbus.o later.
diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801bx/chip.h
similarity index 85%
copy from src/southbridge/intel/i82801xx/chip.h
copy to src/southbridge/intel/i82801bx/chip.h
index 443df451..a168e85 100644
--- a/src/southbridge/intel/i82801xx/chip.h
+++ b/src/southbridge/intel/i82801bx/chip.h
@@ -19,7 +19,7 @@
*/
/*
- * The i82801xx code currently supports:
+ * The i82801bx code currently supports:
* - 82801AA
* - 82801AB
* - 82801BA
@@ -32,10 +32,10 @@
* This code should NOT be used for ICH6 and later versions.
*/
-#ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
-#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
+#ifndef SOUTHBRIDGE_INTEL_I82801BX_CHIP_H
+#define SOUTHBRIDGE_INTEL_I82801BX_CHIP_H
-struct southbridge_intel_i82801xx_config {
+struct southbridge_intel_i82801bx_config {
/**
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
@@ -53,6 +53,6 @@
uint8_t ide1_enable;
};
-extern struct chip_operations southbridge_intel_i82801xx_ops;
+extern struct chip_operations southbridge_intel_i82801bx_ops;
#endif
diff --git a/src/southbridge/intel/i82801xx/cmos_failover.c b/src/southbridge/intel/i82801bx/cmos_failover.c
similarity index 97%
copy from src/southbridge/intel/i82801xx/cmos_failover.c
copy to src/southbridge/intel/i82801bx/cmos_failover.c
index 9307f40..d2e4081 100644
--- a/src/southbridge/intel/i82801xx/cmos_failover.c
+++ b/src/southbridge/intel/i82801bx/cmos_failover.c
@@ -16,7 +16,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include "i82801xx.h"
+#include "i82801bx.h"
static void check_cmos_failed(void)
{
diff --git a/src/southbridge/intel/i82801xx/i82801xx.c b/src/southbridge/intel/i82801bx/i82801bx.c
similarity index 90%
copy from src/southbridge/intel/i82801xx/i82801xx.c
copy to src/southbridge/intel/i82801bx/i82801bx.c
index 385b122..2352723 100644
--- a/src/southbridge/intel/i82801xx/i82801xx.c
+++ b/src/southbridge/intel/i82801bx/i82801bx.c
@@ -23,9 +23,9 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include "i82801xx.h"
+#include "i82801bx.h"
-void i82801xx_enable(device_t dev)
+void i82801bx_enable(device_t dev)
{
unsigned int index = 0;
uint16_t cur_disable_mask, new_disable_mask;
@@ -61,7 +61,7 @@
}
}
-struct chip_operations southbridge_intel_i82801xx_ops = {
- CHIP_NAME("Intel 82801 Series Southbridge")
- .enable_dev = i82801xx_enable,
+struct chip_operations southbridge_intel_i82801bx_ops = {
+ CHIP_NAME("Intel ICH2 (82801Bx) Series Southbridge")
+ .enable_dev = i82801bx_enable,
};
diff --git a/src/southbridge/intel/i82801xx/i82801xx.h b/src/southbridge/intel/i82801bx/i82801bx.h
similarity index 94%
copy from src/southbridge/intel/i82801xx/i82801xx.h
copy to src/southbridge/intel/i82801bx/i82801bx.h
index d90cc32..9705bee 100644
--- a/src/southbridge/intel/i82801xx/i82801xx.h
+++ b/src/southbridge/intel/i82801bx/i82801bx.h
@@ -18,12 +18,12 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
-#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
+#ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
+#define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
-extern void i82801xx_enable(device_t dev);
+extern void i82801bx_enable(device_t dev);
#endif
#define PCI_DMA_CFG 0x90
@@ -117,4 +117,5 @@
/* HPET, if present */
#define HPET_ADDR 0xfed0000
-#endif /* SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H */
+#endif /* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */
+
diff --git a/src/southbridge/intel/i82801xx/i82801xx_ac97.c b/src/southbridge/intel/i82801bx/i82801bx_ac97.c
similarity index 98%
copy from src/southbridge/intel/i82801xx/i82801xx_ac97.c
copy to src/southbridge/intel/i82801bx/i82801bx_ac97.c
index ace04ff..2966d20 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_ac97.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_ac97.c
@@ -25,7 +25,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801bx.h"
static struct device_operations ac97_ops = {
.read_resources = pci_dev_read_resources,
@@ -33,7 +33,7 @@
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801bx_enable,
};
/* 82801AA (ICH) */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c
similarity index 96%
copy from src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
copy to src/southbridge/intel/i82801bx/i82801bx_early_lpc.c
index 3ae91d7..b64c3d8 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c
@@ -18,7 +18,7 @@
*
*/
-static void i82801xx_halt_tco_timer(void)
+static void i82801bx_halt_tco_timer(void)
{
device_t dev;
uint16_t halt_tco_timer;
diff --git a/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c b/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
similarity index 97%
rename from src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
rename to src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
index d1bd051..b8ec9b7 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c
@@ -21,8 +21,8 @@
*/
#include <device/pci_ids.h>
-#include "i82801xx.h"
-#include "i82801xx_smbus.h"
+#include "i82801bx.h"
+#include "i82801bx_smbus.h"
static void enable_smbus(void)
{
diff --git a/src/southbridge/intel/i82801xx/i82801xx_ide.c b/src/southbridge/intel/i82801bx/i82801bx_ide.c
similarity index 96%
copy from src/southbridge/intel/i82801xx/i82801xx_ide.c
copy to src/southbridge/intel/i82801bx/i82801bx_ide.c
index 4173cc6..9bfab00 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_ide.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_ide.c
@@ -25,9 +25,9 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801bx.h"
-typedef struct southbridge_intel_i82801xx_config config_t;
+typedef struct southbridge_intel_i82801bx_config config_t;
static void ide_init(struct device *dev)
{
@@ -67,7 +67,7 @@
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801bx_enable,
};
/* 82801AA */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
similarity index 91%
rename from src/southbridge/intel/i82801xx/i82801xx_lpc.c
rename to src/southbridge/intel/i82801bx/i82801bx_lpc.c
index f7fae37..4691ed4 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_lpc.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
@@ -30,13 +30,13 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
-#include "i82801xx.h"
+#include "i82801bx.h"
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
#define NMI_OFF 0
-typedef struct southbridge_intel_i82801xx_config config_t;
+typedef struct southbridge_intel_i82801bx_config config_t;
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@@ -74,7 +74,7 @@
* specific IRQ values in your mainboards Config.lb.
*/
-void i82801xx_enable_apic(struct device *dev)
+void i82801bx_enable_apic(struct device *dev)
{
uint32_t reg32;
volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
@@ -108,7 +108,7 @@
*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
}
-void i82801xx_enable_serial_irqs(struct device *dev)
+void i82801bx_enable_serial_irqs(struct device *dev)
{
/* Set packet length and toggle silent mode bit. */
pci_write_config8(dev, SERIRQ_CNTL,
@@ -118,7 +118,7 @@
/* TODO: Explain/#define the real meaning of these magic numbers. */
}
-static void i82801xx_pirq_init(device_t dev, uint16_t ich_model)
+static void i82801bx_pirq_init(device_t dev, uint16_t ich_model)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -176,7 +176,7 @@
}
}
-static void i82801xx_power_options(device_t dev)
+static void i82801bx_power_options(device_t dev)
{
uint8_t byte;
int pwr_on = -1;
@@ -220,7 +220,7 @@
}
}
-void i82801xx_rtc_init(struct device *dev)
+void i82801bx_rtc_init(struct device *dev)
{
uint8_t reg8;
uint32_t reg32;
@@ -240,7 +240,7 @@
pci_write_config8(dev, RTC_CONF, 0x04);
}
-void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask)
+void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask)
{
uint16_t reg16;
int i;
@@ -255,7 +255,7 @@
pci_write_config16(dev, PCI_DMA_CFG, reg16);
}
-static void i82801xx_lpc_decode_en(device_t dev, uint16_t ich_model)
+static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model)
{
/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
@@ -302,36 +302,36 @@
pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
- i82801xx_enable_apic(dev);
+ i82801bx_enable_apic(dev);
- i82801xx_enable_serial_irqs(dev);
+ i82801bx_enable_serial_irqs(dev);
/* Setup the PIRQ. */
- i82801xx_pirq_init(dev, ich_model);
+ i82801bx_pirq_init(dev, ich_model);
/* Setup power options. */
- i82801xx_power_options(dev);
+ i82801bx_power_options(dev);
/* Set the state of the GPIO lines. */
gpio_init(dev, ich_model);
/* Initialize the real time clock. */
- i82801xx_rtc_init(dev);
+ i82801bx_rtc_init(dev);
/* Route DMA. */
- i82801xx_lpc_route_dma(dev, 0xff);
+ i82801bx_lpc_route_dma(dev, 0xff);
/* Initialize ISA DMA. */
isa_dma_init();
/* Setup decode ports and LPC I/F enables. */
- i82801xx_lpc_decode_en(dev, ich_model);
+ i82801bx_lpc_decode_en(dev, ich_model);
/* Initialize the High Precision Event Timers, if present. */
enable_hpet(dev);
}
-static void i82801xx_lpc_read_resources(device_t dev)
+static void i82801bx_lpc_read_resources(device_t dev)
{
struct resource *res;
@@ -357,19 +357,19 @@
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void i82801xx_lpc_enable_resources(device_t dev)
+static void i82801bx_lpc_enable_resources(device_t dev)
{
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static struct device_operations lpc_ops = {
- .read_resources = i82801xx_lpc_read_resources,
+ .read_resources = i82801bx_lpc_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = i82801xx_lpc_enable_resources,
+ .enable_resources = i82801bx_lpc_enable_resources,
.init = lpc_init,
.scan_bus = scan_static_bus,
- .enable = i82801xx_enable,
+ .enable = i82801bx_enable,
};
static const struct pci_driver i82801aa_lpc __pci_driver = {
diff --git a/src/southbridge/intel/i82801xx/i82801xx_nic.c b/src/southbridge/intel/i82801bx/i82801bx_nic.c
similarity index 100%
copy from src/southbridge/intel/i82801xx/i82801xx_nic.c
copy to src/southbridge/intel/i82801bx/i82801bx_nic.c
diff --git a/src/southbridge/intel/i82801xx/i82801xx_pci.c b/src/southbridge/intel/i82801bx/i82801bx_pci.c
similarity index 100%
copy from src/southbridge/intel/i82801xx/i82801xx_pci.c
copy to src/southbridge/intel/i82801bx/i82801bx_pci.c
diff --git a/src/southbridge/intel/i82801xx/i82801xx_reset.c b/src/southbridge/intel/i82801bx/i82801bx_reset.c
similarity index 100%
copy from src/southbridge/intel/i82801xx/i82801xx_reset.c
copy to src/southbridge/intel/i82801bx/i82801bx_reset.c
diff --git a/src/southbridge/intel/i82801xx/i82801xx_sata.c b/src/southbridge/intel/i82801bx/i82801bx_sata.c
similarity index 97%
rename from src/southbridge/intel/i82801xx/i82801xx_sata.c
rename to src/southbridge/intel/i82801bx/i82801bx_sata.c
index de8b3b0..19a892a 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_sata.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_sata.c
@@ -23,7 +23,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801bx.h"
/* TODO: Set dynamically, if the user only wants one SATA channel or none
* at all.
@@ -64,7 +64,7 @@
.enable_resources = pci_dev_enable_resources,
.init = sata_init,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801bx_enable,
};
/* 82801EB */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_smbus.c b/src/southbridge/intel/i82801bx/i82801bx_smbus.c
similarity index 98%
rename from src/southbridge/intel/i82801xx/i82801xx_smbus.c
rename to src/southbridge/intel/i82801bx/i82801bx_smbus.c
index 1608650..8a5476f 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_smbus.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.c
@@ -24,7 +24,7 @@
#include <smbus.h>
#include <pci.h>
#include <arch/io.h>
-#include "i82801xx.h"
+#include "i82801bx.h"
#include "i82801_smbus.h"
static int smbus_read_byte(struct bus *bus, device_t dev, u8 address)
diff --git a/src/southbridge/intel/i82801xx/i82801xx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h
similarity index 100%
copy from src/southbridge/intel/i82801xx/i82801xx_smbus.h
copy to src/southbridge/intel/i82801bx/i82801bx_smbus.h
diff --git a/src/southbridge/intel/i82801xx/i82801xx_usb.c b/src/southbridge/intel/i82801bx/i82801bx_usb.c
similarity index 98%
copy from src/southbridge/intel/i82801xx/i82801xx_usb.c
copy to src/southbridge/intel/i82801bx/i82801bx_usb.c
index 74bbbee..721f5bf 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_usb.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_usb.c
@@ -24,7 +24,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801bx.h"
static void usb_init(struct device *dev)
{
@@ -37,7 +37,7 @@
.enable_resources = pci_dev_enable_resources,
.init = usb_init,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801bx_enable,
};
/* 82801AA (ICH) */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c b/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c
similarity index 97%
rename from src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
rename to src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c
index 032f198..1e885e9 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c
@@ -23,7 +23,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801xx.h"
+#include "i82801bx.h"
static void usb_ehci_init(struct device *dev)
{
@@ -65,7 +65,7 @@
.enable_resources = pci_dev_enable_resources,
.init = usb_ehci_init,
.scan_bus = 0,
- .enable = i82801xx_enable,
+ .enable = i82801bx_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/intel/i82801xx/i82801xx_watchdog.c b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c
similarity index 100%
copy from src/southbridge/intel/i82801xx/i82801xx_watchdog.c
copy to src/southbridge/intel/i82801bx/i82801bx_watchdog.c
diff --git a/src/southbridge/intel/i82801ca/Kconfig b/src/southbridge/intel/i82801ca/Kconfig
deleted file mode 100644
index c5404e9..0000000
--- a/src/southbridge/intel/i82801ca/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-config SOUTHBRIDGE_INTEL_I82801CA
- bool
diff --git a/src/southbridge/intel/i82801ca/Makefile.inc b/src/southbridge/intel/i82801ca/Makefile.inc
deleted file mode 100644
index 587b067..0000000
--- a/src/southbridge/intel/i82801ca/Makefile.inc
+++ /dev/null
@@ -1,8 +0,0 @@
-driver-y += i82801ca.o
-driver-y += i82801ca_usb.o
-driver-y += i82801ca_lpc.o
-driver-y += i82801ca_ide.o
-driver-y += i82801ca_ac97.o
-#driver-y += i82801ca_nic.o
-driver-y += i82801ca_pci.o
-obj-y += i82801ca_reset.o
diff --git a/src/southbridge/intel/i82801ca/chip.h b/src/southbridge/intel/i82801ca/chip.h
deleted file mode 100644
index f9583ca..0000000
--- a/src/southbridge/intel/i82801ca/chip.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef I82801CA_CHIP_H
-#define I82801CA_CHIP_H
-
-struct southbridge_intel_i82801ca_config
-{
-};
-extern struct chip_operations southbridge_intel_i82801ca_ops;
-
-#endif /* I82801CA_CHIP_H */
diff --git a/src/southbridge/intel/i82801cx/Kconfig b/src/southbridge/intel/i82801cx/Kconfig
new file mode 100644
index 0000000..a0c775d
--- /dev/null
+++ b/src/southbridge/intel/i82801cx/Kconfig
@@ -0,0 +1,2 @@
+config SOUTHBRIDGE_INTEL_I82801CX
+ bool
diff --git a/src/southbridge/intel/i82801cx/Makefile.inc b/src/southbridge/intel/i82801cx/Makefile.inc
new file mode 100644
index 0000000..163c072
--- /dev/null
+++ b/src/southbridge/intel/i82801cx/Makefile.inc
@@ -0,0 +1,8 @@
+driver-y += i82801cx.o
+driver-y += i82801cx_usb.o
+driver-y += i82801cx_lpc.o
+driver-y += i82801cx_ide.o
+driver-y += i82801cx_ac97.o
+#driver-y += i82801cx_nic.o
+driver-y += i82801cx_pci.o
+obj-y += i82801cx_reset.o
diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h
new file mode 100644
index 0000000..99b069e
--- /dev/null
+++ b/src/southbridge/intel/i82801cx/chip.h
@@ -0,0 +1,9 @@
+#ifndef I82801CX_CHIP_H
+#define I82801CX_CHIP_H
+
+struct southbridge_intel_i82801cx_config
+{
+};
+extern struct chip_operations southbridge_intel_i82801cx_ops;
+
+#endif /* I82801CX_CHIP_H */
diff --git a/src/southbridge/intel/i82801ca/cmos_failover.c b/src/southbridge/intel/i82801cx/cmos_failover.c
similarity index 94%
rename from src/southbridge/intel/i82801ca/cmos_failover.c
rename to src/southbridge/intel/i82801cx/cmos_failover.c
index bf35764..ab1816f 100644
--- a/src/southbridge/intel/i82801ca/cmos_failover.c
+++ b/src/southbridge/intel/i82801cx/cmos_failover.c
@@ -1,6 +1,6 @@
//kind of cmos_err for ich3
-#include "i82801ca.h"
+#include "i82801cx.h"
static void check_cmos_failed(void)
{
diff --git a/src/southbridge/intel/i82801ca/i82801ca.c b/src/southbridge/intel/i82801cx/i82801cx.c
similarity index 86%
rename from src/southbridge/intel/i82801ca/i82801ca.c
rename to src/southbridge/intel/i82801cx/i82801cx.c
index 23a64f7..ddbbc7d 100644
--- a/src/southbridge/intel/i82801ca/i82801ca.c
+++ b/src/southbridge/intel/i82801cx/i82801cx.c
@@ -3,9 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <assert.h>
-#include "i82801ca.h"
+#include "i82801cx.h"
-void i82801ca_enable(device_t dev)
+void i82801cx_enable(device_t dev)
{
unsigned int index = 0;
uint8_t bHasDisableBit = 0;
@@ -47,7 +47,7 @@
}
}
-struct chip_operations southbridge_intel_i82801ca_ops = {
- CHIP_NAME("Intel 82801CA Southbridge")
- .enable_dev = i82801ca_enable,
+struct chip_operations southbridge_intel_i82801cx_ops = {
+ CHIP_NAME("Intel ICH3 (82801Cx) Series Southbridge")
+ .enable_dev = i82801cx_enable,
};
diff --git a/src/southbridge/intel/i82801ca/i82801ca.h b/src/southbridge/intel/i82801cx/i82801cx.h
similarity index 94%
rename from src/southbridge/intel/i82801ca/i82801ca.h
rename to src/southbridge/intel/i82801cx/i82801cx.h
index a761056..b9b3511 100644
--- a/src/southbridge/intel/i82801ca/i82801ca.h
+++ b/src/southbridge/intel/i82801cx/i82801cx.h
@@ -1,9 +1,9 @@
-#ifndef I82801CA_H
-#define I82801CA_H
+#ifndef I82801CX_H
+#define I82801CX_H
#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
#include "chip.h"
-extern void i82801ca_enable(device_t dev);
+extern void i82801cx_enable(device_t dev);
#endif
@@ -75,4 +75,4 @@
*/
#define SMBUS_TIMEOUT (100*1000)
-#endif /* I82801CA_H */
+#endif /* I82801CX_H */
diff --git a/src/southbridge/intel/i82801ca/i82801ca_ac97.c b/src/southbridge/intel/i82801cx/i82801cx_ac97.c
similarity index 90%
rename from src/southbridge/intel/i82801ca/i82801ca_ac97.c
rename to src/southbridge/intel/i82801cx/i82801cx_ac97.c
index 7e03cc3..5de44fc 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_ac97.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_ac97.c
@@ -6,14 +6,14 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801ca.h"
+#include "i82801cx.h"
static struct device_operations ac97audio_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = i82801ca_enable,
+ .enable = i82801cx_enable,
.init = 0,
.scan_bus = 0,
};
@@ -29,7 +29,7 @@
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = i82801ca_enable,
+ .enable = i82801cx_enable,
.init = 0,
.scan_bus = 0,
};
diff --git a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
similarity index 98%
rename from src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
rename to src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
index d33e404..9c34802 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c
@@ -1,5 +1,5 @@
#include <device/pci_ids.h>
-#include "i82801ca.h"
+#include "i82801cx.h"
static void enable_smbus(void)
{
diff --git a/src/southbridge/intel/i82801ca/i82801ca_ide.c b/src/southbridge/intel/i82801cx/i82801cx_ide.c
similarity index 95%
rename from src/southbridge/intel/i82801ca/i82801ca_ide.c
rename to src/southbridge/intel/i82801cx/i82801cx_ide.c
index d1a19c7..2506b2f 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_ide.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_ide.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801ca.h"
+#include "i82801cx.h"
static void ide_init(struct device *dev)
@@ -38,7 +38,7 @@
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.scan_bus = 0,
- .enable = i82801ca_enable,
+ .enable = i82801cx_enable,
};
static const struct pci_driver ide_driver __pci_driver = {
diff --git a/src/southbridge/intel/i82801ca/i82801ca_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
similarity index 90%
rename from src/southbridge/intel/i82801ca/i82801ca_lpc.c
rename to src/southbridge/intel/i82801cx/i82801cx_lpc.c
index fd16fef..4785242 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_lpc.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
@@ -11,7 +11,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
-#include "i82801ca.h"
+#include "i82801cx.h"
#define NMI_OFF 0
@@ -23,7 +23,7 @@
#define MAINBOARD_POWER_ON 1
-void i82801ca_enable_ioapic( struct device *dev)
+void i82801cx_enable_ioapic( struct device *dev)
{
uint32_t dword;
volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000;
@@ -54,14 +54,14 @@
}
// This is how interrupts are received from the Super I/O chip
-void i82801ca_enable_serial_irqs( struct device *dev)
+void i82801cx_enable_serial_irqs( struct device *dev)
{
// Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
}
//----------------------------------------------------------------------------------
-// Function: i82801ca_lpc_route_dma
+// Function: i82801cx_lpc_route_dma
// Parameters: dev
// mask - identifies whether each channel should be used for PCI DMA
// (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
@@ -69,7 +69,7 @@
// Return Value: None
// Description: Route all DMA channels to either PCI or LPC.
//
-void i82801ca_lpc_route_dma( struct device *dev, uint8_t mask)
+void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
{
uint16_t dmaConfig;
int channelIndex;
@@ -84,7 +84,7 @@
pci_write_config16(dev, PCI_DMA_CFG, dmaConfig);
}
-void i82801ca_rtc_init(struct device *dev)
+void i82801cx_rtc_init(struct device *dev)
{
uint32_t dword;
int rtc_failed;
@@ -116,7 +116,7 @@
}
-void i82801ca_1f0_misc(struct device *dev)
+void i82801cx_1f0_misc(struct device *dev)
{
// Prevent LPC disabling, enable parity errors, and SERR# (System Error)
pci_write_config16(dev, PCI_COMMAND, 0x014f);
@@ -161,9 +161,9 @@
int nmi_option;
/* IO APIC initialization */
- i82801ca_enable_ioapic(dev);
+ i82801cx_enable_ioapic(dev);
- i82801ca_enable_serial_irqs(dev);
+ i82801cx_enable_serial_irqs(dev);
/* power after power fail */
/* FIXME this doesn't work! */
@@ -193,17 +193,17 @@
}
/* Initialize the real time clock */
- i82801ca_rtc_init(dev);
+ i82801cx_rtc_init(dev);
- i82801ca_lpc_route_dma(dev, 0xff);
+ i82801cx_lpc_route_dma(dev, 0xff);
/* Initialize isa dma */
isa_dma_init();
- i82801ca_1f0_misc(dev);
+ i82801cx_1f0_misc(dev);
}
-static void i82801ca_lpc_read_resources(device_t dev)
+static void i82801cx_lpc_read_resources(device_t dev)
{
struct resource *res;
@@ -229,16 +229,16 @@
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void i82801ca_lpc_enable_resources(device_t dev)
+static void i82801cx_lpc_enable_resources(device_t dev)
{
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static struct device_operations lpc_ops = {
- .read_resources = i82801ca_lpc_read_resources,
+ .read_resources = i82801cx_lpc_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = i82801ca_lpc_enable_resources,
+ .enable_resources = i82801cx_lpc_enable_resources,
.init = lpc_init,
.scan_bus = scan_static_bus,
.enable = 0,
diff --git a/src/southbridge/intel/i82801ca/i82801ca_nic.c b/src/southbridge/intel/i82801cx/i82801cx_nic.c
similarity index 95%
rename from src/southbridge/intel/i82801ca/i82801ca_nic.c
rename to src/southbridge/intel/i82801cx/i82801cx_nic.c
index c0b01bc..00ce038 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_nic.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_nic.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801ca.h"
+#include "i82801cx.h"
static struct device_operations nic_ops = {
diff --git a/src/southbridge/intel/i82801ca/i82801ca_pci.c b/src/southbridge/intel/i82801cx/i82801cx_pci.c
similarity index 96%
rename from src/southbridge/intel/i82801ca/i82801ca_pci.c
rename to src/southbridge/intel/i82801cx/i82801cx_pci.c
index 5f7b897..842b214 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_pci.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_pci.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801ca.h"
+#include "i82801cx.h"
static void pci_init(struct device *dev)
{
diff --git a/src/southbridge/intel/i82801ca/i82801ca_reset.c b/src/southbridge/intel/i82801cx/i82801cx_reset.c
similarity index 83%
rename from src/southbridge/intel/i82801ca/i82801ca_reset.c
rename to src/southbridge/intel/i82801cx/i82801cx_reset.c
index 93ef6d9..20e8530 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_reset.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_reset.c
@@ -1,6 +1,6 @@
#include <arch/io.h>
-void i82801ca_hard_reset(void)
+void i82801cx_hard_reset(void)
{
/* Try rebooting through port 0xcf9 */
// Hard reset without power cycle
diff --git a/src/southbridge/intel/i82801ca/i82801ca_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_smbus.c
similarity index 98%
rename from src/southbridge/intel/i82801ca/i82801ca_smbus.c
rename to src/southbridge/intel/i82801cx/i82801cx_smbus.c
index 0eceba7..b69bbc1 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_smbus.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_smbus.c
@@ -1,7 +1,7 @@
#include <smbus.h>
#include <pci.h>
#include <arch/io.h>
-#include "i82801ca.h"
+#include "i82801cx.h"
#define PM_BUS 0
#define PM_DEVFN PCI_DEVFN(0x1f,3)
diff --git a/src/southbridge/intel/i82801ca/i82801ca_usb.c b/src/southbridge/intel/i82801cx/i82801cx_usb.c
similarity index 94%
rename from src/southbridge/intel/i82801ca/i82801ca_usb.c
rename to src/southbridge/intel/i82801cx/i82801cx_usb.c
index 7e7c058..258581a 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_usb.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_usb.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801ca.h"
+#include "i82801cx.h"
static void usb_init(struct device *dev)
{
@@ -28,7 +28,7 @@
.enable_resources = pci_dev_enable_resources,
.init = usb_init,
.scan_bus = 0,
- .enable = i82801ca_enable,
+ .enable = i82801cx_enable,
};
static const struct pci_driver usb_driver_1 __pci_driver = {
diff --git a/src/southbridge/intel/i82801dbm/Kconfig b/src/southbridge/intel/i82801dbm/Kconfig
deleted file mode 100644
index 3433d59..0000000
--- a/src/southbridge/intel/i82801dbm/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-config SOUTHBRIDGE_INTEL_I82801DBM
- bool
diff --git a/src/southbridge/intel/i82801dbm/Makefile.inc b/src/southbridge/intel/i82801dbm/Makefile.inc
deleted file mode 100644
index 7134279..0000000
--- a/src/southbridge/intel/i82801dbm/Makefile.inc
+++ /dev/null
@@ -1,9 +0,0 @@
-driver-y += i82801dbm.o
-driver-y += i82801dbm_usb.o
-driver-y += i82801dbm_lpc.o
-driver-y += i82801dbm_ide.o
-driver-y += i82801dbm_usb2.o
-driver-y += i82801dbm_ac97.o
-#driver-y += i82801dbm_nic.o
-#driver-y += i82801dbm_pci.o
-obj-y += i82801dbm_reset.o
diff --git a/src/southbridge/intel/i82801dbm/chip.h b/src/southbridge/intel/i82801dbm/chip.h
deleted file mode 100644
index e1e3da0..0000000
--- a/src/southbridge/intel/i82801dbm/chip.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef I82801DBM_CHIP_H
-#define I82801DBM_CHIP_H
-
-struct southbridge_intel_i82801dbm_config
-{
- int enable_usb;
- int enable_native_ide;
-};
-struct chip_operations;
-extern struct chip_operations southbridge_intel_i82801dbm_ops;
-
-#endif /* I82801DBM_CHIP_H */
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm.h b/src/southbridge/intel/i82801dbm/i82801dbm.h
deleted file mode 100644
index 824d23a..0000000
--- a/src/southbridge/intel/i82801dbm/i82801dbm.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
- * fb1 code is what we want, fb2 structure is needed however.
- * so we need to get fb1 code for 82801dbm into fb2 structure.
- */
-/* What I did: took the 80801er stuff from fb2, verify it against the
- * db stuff in fb1, and made sure it was right.
- */
-
-#ifndef I82801DBM_H
-#define I82801DBM_H
-
-#include "chip.h"
-extern void i82801dbm_enable(device_t dev);
-
-/*
-000 = Non-combined. P0 is primary master. P1 is secondary master.
-001 = Non-combined. P0 is secondary master. P1 is primary master.
-100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel
-disabled.
-101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
-110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE
-channel disabled.
-111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
-*/
-
-#define PCI_DMA_CFG 0x90
-#define SERIRQ_CNTL 0x64
-#define GEN_CNTL 0xd0
-#define GEN_STS 0xd4
-#define RTC_CONF 0xd8
-#define GEN_PMCON_3 0xa4
-
-#define PCICMD 0x04
-#define PMBASE 0x40
-#define ACPI_CNTL 0x44
-#define BIOS_CNTL 0x4E
-#define GPIO_BASE 0x58
-#define GPIO_CNTL 0x5C
-#define PIRQA_ROUT 0x60
-#define PIRQE_ROUT 0x68
-#define COM_DEC 0xE0
-#define LPC_EN 0xE6
-#define FUNC_DIS 0xF2
-
-/* 1e f0 244e */
-
-#define CMD 0x04
-#define SBUS_NUM 0x19
-#define SUB_BUS_NUM 0x1A
-#define SMLT 0x1B
-#define IOBASE 0x1C
-#define IOLIM 0x1D
-#define MEMBASE 0x20
-#define MEMLIM 0x22
-#define CNF 0x50
-#define MTT 0x70
-#define PCI_MAST_STS 0x82
-
-#define RTC_FAILED (1 <<2)
-
-
-#define SMBUS_IO_BASE 0x1000
-
-#define SMBHSTSTAT 0x0
-#define SMBHSTCTL 0x2
-#define SMBHSTCMD 0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT 0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
-
-/* Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-#define SMBUS_TIMEOUT (100*1000)
-
-#endif /* I82801DBM_H */
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
new file mode 100644
index 0000000..6a35691
--- /dev/null
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -0,0 +1,2 @@
+config SOUTHBRIDGE_INTEL_I82801DX
+ bool
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
new file mode 100644
index 0000000..7167e1d
--- /dev/null
+++ b/src/southbridge/intel/i82801dx/Makefile.inc
@@ -0,0 +1,9 @@
+driver-y += i82801dx.o
+driver-y += i82801dx_usb.o
+driver-y += i82801dx_lpc.o
+driver-y += i82801dx_ide.o
+driver-y += i82801dx_usb2.o
+driver-y += i82801dx_ac97.o
+#driver-y += i82801dx_nic.o
+#driver-y += i82801dx_pci.o
+obj-y += i82801dx_reset.o
diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h
new file mode 100644
index 0000000..fdbb7d2
--- /dev/null
+++ b/src/southbridge/intel/i82801dx/chip.h
@@ -0,0 +1,27 @@
+#ifndef I82801DX_CHIP_H
+#define I82801DX_CHIP_H
+
+struct southbridge_intel_i82801dx_config
+{
+ int enable_usb;
+ int enable_native_ide;
+ /**
+ * Interrupt Routing configuration
+ * If bit7 is 1, the interrupt is disabled.
+ */
+ uint8_t pirqa_routing;
+ uint8_t pirqb_routing;
+ uint8_t pirqc_routing;
+ uint8_t pirqd_routing;
+ uint8_t pirqe_routing;
+ uint8_t pirqf_routing;
+ uint8_t pirqg_routing;
+ uint8_t pirqh_routing;
+
+ uint8_t ide0_enable;
+ uint8_t ide1_enable;
+};
+
+extern struct chip_operations southbridge_intel_i82801dx_ops;
+
+#endif /* I82801DBM_CHIP_H */
diff --git a/src/southbridge/intel/i82801dbm/cmos_failover.c b/src/southbridge/intel/i82801dx/cmos_failover.c
similarity index 100%
rename from src/southbridge/intel/i82801dbm/cmos_failover.c
rename to src/southbridge/intel/i82801dx/cmos_failover.c
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm.c b/src/southbridge/intel/i82801dx/i82801dx.c
similarity index 86%
rename from src/southbridge/intel/i82801dbm/i82801dbm.c
rename to src/southbridge/intel/i82801dx/i82801dx.c
index 157ffca..abfd8c2 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm.c
+++ b/src/southbridge/intel/i82801dx/i82801dx.c
@@ -2,9 +2,9 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801dbm.h"
+#include "i82801dx.h"
-void i82801dbm_enable(device_t dev)
+void i82801dx_enable(device_t dev)
{
unsigned int index = 0;
uint8_t bHasDisableBit = 0;
@@ -59,7 +59,7 @@
}
}
-struct chip_operations southbridge_intel_i82801dbm_ops = {
- CHIP_NAME("Intel 82801DBM Southbridge")
- .enable_dev = i82801dbm_enable,
+struct chip_operations southbridge_intel_i82801dx_ops = {
+ CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge")
+ .enable_dev = i82801dx_enable,
};
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
new file mode 100644
index 0000000..d4e1aa0
--- /dev/null
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -0,0 +1,163 @@
+/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
+ * fb1 code is what we want, fb2 structure is needed however.
+ * so we need to get fb1 code for 82801dbm into fb2 structure.
+ */
+/* What I did: took the 80801er stuff from fb2, verify it against the
+ * db stuff in fb1, and made sure it was right.
+ */
+
+#ifndef I82801DX_H
+#define I82801DX_H
+
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAM__)
+#include "chip.h"
+extern void i82801dx_enable(device_t dev);
+#endif
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_KEEP 2
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+/*
+000 = Non-combined. P0 is primary master. P1 is secondary master.
+001 = Non-combined. P0 is secondary master. P1 is primary master.
+100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel
+disabled.
+101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
+110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE
+channel disabled.
+111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
+*/
+
+#define PCI_DMA_CFG 0x90
+#define SERIRQ_CNTL 0x64
+#define GEN_CNTL 0xd0
+#define GEN_STS 0xd4
+#define RTC_CONF 0xd8
+#define GEN_PMCON_3 0xa4
+
+#define PCICMD 0x04
+#define PMBASE 0x40
+#define PMBASE_ADDR 0x0400
+#define ACPI_CNTL 0x44
+#define BIOS_CNTL 0x4E
+#define GPIO_BASE 0x58
+#define GPIO_CNTL 0x5C
+#define PIRQA_ROUT 0x60
+#define PIRQE_ROUT 0x68
+#define COM_DEC 0xE0
+#define LPC_EN 0xE6
+#define FUNC_DIS 0xF2
+
+/* 1e f0 244e */
+
+#define CMD 0x04
+#define SBUS_NUM 0x19
+#define SUB_BUS_NUM 0x1A
+#define SMLT 0x1B
+#define IOBASE 0x1C
+#define IOLIM 0x1D
+#define MEMBASE 0x20
+#define MEMLIM 0x22
+#define CNF 0x50
+#define MTT 0x70
+#define PCI_MAST_STS 0x82
+
+#define RTC_FAILED (1 <<2)
+
+
+#define SMBUS_IO_BASE 0x1000
+
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL 0x2
+#define SMBHSTCMD 0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT 0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL 0xf
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000)
+
+#define PM1_STS 0x00
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define BM_STS (1 << 4)
+#define TMROF_STS (1 << 0)
+#define PM1_EN 0x02
+#define PCIEXPWAK_DIS (1 << 14)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
+#define PM1_CNT 0x04
+#define SLP_EN (1 << 13)
+#define SLP_TYP (7 << 10)
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define PROC_CNT 0x10
+#define LV2 0x14
+#define LV3 0x15
+#define LV4 0x16
+#define PM2_CNT 0x20 // mobile only
+#define GPE0_STS 0x28
+#define PME_B0_STS (1 << 13)
+#define USB3_STS (1 << 12)
+#define PME_STS (1 << 11)
+#define BATLOW_STS (1 << 10)
+#define GST_STS (1 << 9)
+#define RI_STS (1 << 8)
+#define SMB_WAK_STS (1 << 7)
+#define TCOSCI_STS (1 << 6)
+#define AC97_STS (1 << 5)
+#define USB2_STS (1 << 4)
+#define USB1_STS (1 << 3)
+#define SWGPE_STS (1 << 2)
+#define HOT_PLUG_STS (1 << 1)
+#define THRM_STS (1 << 0)
+#define GPE0_EN 0x2c
+#define PME_B0_EN (1 << 13)
+#define PME_EN (1 << 11)
+#define SMI_EN 0x30
+#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
+#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
+#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define MCSMI_EN (1 << 11) // Trap microcontroller range access
+#define BIOS_RLS (1 << 7) // asserts SCI on bit set
+#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
+#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
+#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
+#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
+#define EOS (1 << 1) // End of SMI (deassert SMI#)
+#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
+#define SMI_STS 0x34
+#define ALT_GP_SMI_EN 0x38
+#define ALT_GP_SMI_STS 0x3a
+#define GPE_CNTL 0x42
+#define DEVACT_STS 0x44
+#define SS_CNT 0x50
+#define C3_RES 0x54
+
+#define TCOBASE 0x60 /* TCO Base Address Register */
+#define TCO1_CNT 0x08 /* TCO1 Control Register */
+
+#endif /* I82801DX_H */
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c b/src/southbridge/intel/i82801dx/i82801dx_ac97.c
similarity index 90%
rename from src/southbridge/intel/i82801dbm/i82801dbm_ac97.c
rename to src/southbridge/intel/i82801dx/i82801dx_ac97.c
index 3b36401..7524498 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_ac97.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_ac97.c
@@ -6,14 +6,14 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801dbm.h"
+#include "i82801dx.h"
static struct device_operations ac97audio_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = i82801dbm_enable,
+ .enable = i82801dx_enable,
.init = 0,
.scan_bus = 0,
};
@@ -29,7 +29,7 @@
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = i82801dbm_enable,
+ .enable = i82801dx_enable,
.init = 0,
.scan_bus = 0,
};
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
similarity index 97%
rename from src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
rename to src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
index a85c08b..0a0ff91 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
@@ -1,6 +1,6 @@
//#define SMBUS_IO_BASE 0x1000
-#define SMBUS_IO_BASE 0x0f00
+//#define SMBUS_IO_BASE 0x0f00
#define SMBHSTSTAT 0x0
#define SMBHSTCTL 0x2
@@ -17,7 +17,7 @@
/* Between 1-10 seconds, We should never timeout normally
* Longer than this is just painful when a timeout condition occurs.
*/
-#define SMBUS_TIMEOUT (100*1000*10)
+//#define SMBUS_TIMEOUT (100*1000*10)
static void enable_smbus(void)
{
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_ide.c b/src/southbridge/intel/i82801dx/i82801dx_ide.c
similarity index 94%
rename from src/southbridge/intel/i82801dbm/i82801dbm_ide.c
rename to src/southbridge/intel/i82801dx/i82801dx_ide.c
index f7d7996..bb35107 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_ide.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_ide.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801dbm.h"
+#include "i82801dx.h"
static void ide_init(struct device *dev)
@@ -42,7 +42,7 @@
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.scan_bus = 0,
- .enable = i82801dbm_enable,
+ .enable = i82801dx_enable,
};
static const struct pci_driver ide_driver __pci_driver = {
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
similarity index 89%
rename from src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
rename to src/southbridge/intel/i82801dx/i82801dx_lpc.c
index c461673..59225d2 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
@@ -10,13 +10,13 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
-#include "i82801dbm.h"
+#include "i82801dx.h"
#define NMI_OFF 0
-void i82801dbm_enable_ioapic( struct device *dev)
+void i82801dx_enable_ioapic( struct device *dev)
{
uint32_t dword;
volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000;
@@ -46,11 +46,11 @@
}
-void i82801dbm_enable_serial_irqs( struct device *dev)
+void i82801dx_enable_serial_irqs( struct device *dev)
{
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
}
-void i82801dbm_lpc_route_dma( struct device *dev, uint8_t mask)
+void i82801dx_lpc_route_dma( struct device *dev, uint8_t mask)
{
uint16_t word;
int i;
@@ -63,7 +63,7 @@
}
pci_write_config16(dev, PCI_DMA_CFG, word);
}
-void i82801dbm_rtc_init(struct device *dev)
+void i82801dx_rtc_init(struct device *dev)
{
uint8_t byte;
uint32_t dword;
@@ -80,7 +80,7 @@
}
-void i82801dbm_1f0_misc(struct device *dev)
+void i82801dx_1f0_misc(struct device *dev)
{
pci_write_config16(dev, PCICMD, 0x014f);
pci_write_config32(dev, PMBASE, 0x00001001);
@@ -122,9 +122,9 @@
int nmi_option;
/* IO APIC initialization */
- i82801dbm_enable_ioapic(dev);
+ i82801dx_enable_ioapic(dev);
- i82801dbm_enable_serial_irqs(dev);
+ i82801dx_enable_serial_irqs(dev);
#ifdef SUSPICIOUS_LOOKING_CODE
// The ICH-4 datasheet does not mention this configuration register.
@@ -166,19 +166,19 @@
}
/* Initialize the real time clock */
- i82801dbm_rtc_init(dev);
+ i82801dx_rtc_init(dev);
- i82801dbm_lpc_route_dma(dev, 0xff);
+ i82801dx_lpc_route_dma(dev, 0xff);
/* Initialize isa dma */
isa_dma_init();
- i82801dbm_1f0_misc(dev);
+ i82801dx_1f0_misc(dev);
/* Initialize the High Precision Event Timers */
enable_hpet(dev);
}
-static void i82801dbm_lpc_read_resources(device_t dev)
+static void i82801dx_lpc_read_resources(device_t dev)
{
struct resource *res;
@@ -204,19 +204,19 @@
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void i82801dbm_lpc_enable_resources(device_t dev)
+static void i82801dx_lpc_enable_resources(device_t dev)
{
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
static struct device_operations lpc_ops = {
- .read_resources = i82801dbm_lpc_read_resources,
+ .read_resources = i82801dx_lpc_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = i82801dbm_lpc_enable_resources,
+ .enable_resources = i82801dx_lpc_enable_resources,
.init = lpc_init,
.scan_bus = scan_static_bus,
- .enable = i82801dbm_enable,
+ .enable = i82801dx_enable,
};
static const struct pci_driver lpc_driver __pci_driver = {
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_nic.c b/src/southbridge/intel/i82801dx/i82801dx_nic.c
similarity index 95%
rename from src/southbridge/intel/i82801dbm/i82801dbm_nic.c
rename to src/southbridge/intel/i82801dx/i82801dx_nic.c
index e25f1bc..6221ba488 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_nic.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_nic.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801dbm.h"
+#include "i82801dx.h"
static struct device_operations nic_ops = {
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_pci.c b/src/southbridge/intel/i82801dx/i82801dx_pci.c
similarity index 96%
rename from src/southbridge/intel/i82801dbm/i82801dbm_pci.c
rename to src/southbridge/intel/i82801dx/i82801dx_pci.c
index b69cd60..0c88bf2 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_pci.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_pci.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801dbm.h"
+#include "i82801dx.h"
static void pci_init(struct device *dev)
{
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_reset.c b/src/southbridge/intel/i82801dx/i82801dx_reset.c
similarity index 100%
rename from src/southbridge/intel/i82801dbm/i82801dbm_reset.c
rename to src/southbridge/intel/i82801dx/i82801dx_reset.c
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_sata.c b/src/southbridge/intel/i82801dx/i82801dx_sata.c
similarity index 96%
rename from src/southbridge/intel/i82801dbm/i82801dbm_sata.c
rename to src/southbridge/intel/i82801dx/i82801dx_sata.c
index 405ee0e..22c6cd7 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_sata.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_sata.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801dbm.h"
+#include "i82801dx.h"
static void sata_init(struct device *dev)
{
@@ -64,7 +64,7 @@
.enable_resources = pci_dev_enable_resources,
.init = sata_init,
.scan_bus = 0,
- .enable = i82801dbm_enable,
+ .enable = i82801dx_enable,
};
static const struct pci_driver stat_driver __pci_driver = {
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_smbus.c
similarity index 97%
rename from src/southbridge/intel/i82801dbm/i82801dbm_smbus.c
rename to src/southbridge/intel/i82801dx/i82801dx_smbus.c
index fd06871..e56a67c 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_smbus.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_smbus.c
@@ -1,3 +1,4 @@
+#include "i82801dx.h"
#include <smbus.h>
#include <pci.h>
#include <arch/io.h>
@@ -5,6 +6,7 @@
#define PM_BUS 0
#define PM_DEVFN PCI_DEVFN(0x1f,3)
+#if 0
#define SMBUS_IO_BASE 0x1000
#define SMBHSTSTAT 0
#define SMBHSTCTL 2
@@ -13,6 +15,7 @@
#define SMBHSTDAT0 5
#define SMBHSTDAT1 6
#define SMBBLKDAT 7
+#endif
void smbus_enable(void)
{
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_usb.c b/src/southbridge/intel/i82801dx/i82801dx_usb.c
similarity index 94%
rename from src/southbridge/intel/i82801dbm/i82801dbm_usb.c
rename to src/southbridge/intel/i82801dx/i82801dx_usb.c
index 3fd6167..2e60193 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_usb.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_usb.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801dbm.h"
+#include "i82801dx.h"
static void usb_init(struct device *dev)
{
@@ -29,7 +29,7 @@
.enable_resources = pci_dev_enable_resources,
.init = usb_init,
.scan_bus = 0,
- .enable = i82801dbm_enable,
+ .enable = i82801dx_enable,
};
static const struct pci_driver usb_driver_1 __pci_driver = {
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c b/src/southbridge/intel/i82801dx/i82801dx_usb2.c
similarity index 93%
rename from src/southbridge/intel/i82801dbm/i82801dbm_usb2.c
rename to src/southbridge/intel/i82801dx/i82801dx_usb2.c
index f05fbbb..ca13e92 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_usb2.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_usb2.c
@@ -5,7 +5,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801dbm.h"
+#include "i82801dx.h"
static void usb2_init(struct device *dev)
{
@@ -30,7 +30,7 @@
.enable_resources = pci_dev_enable_resources,
.init = usb2_init,
.scan_bus = 0,
- .enable = i82801dbm_enable,
+ .enable = i82801dx_enable,
};
static const struct pci_driver usb2_driver __pci_driver = {
diff --git a/src/southbridge/intel/i82801er/Kconfig b/src/southbridge/intel/i82801er/Kconfig
deleted file mode 100644
index adb6c1d..0000000
--- a/src/southbridge/intel/i82801er/Kconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-config SOUTHBRIDGE_INTEL_I82801ER
- bool
- select IOAPIC
diff --git a/src/southbridge/intel/i82801er/Makefile.inc b/src/southbridge/intel/i82801er/Makefile.inc
deleted file mode 100644
index b2f81f8..0000000
--- a/src/southbridge/intel/i82801er/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-driver-y += i82801er.o
-driver-y += i82801er_uhci.o
-driver-y += i82801er_lpc.o
-driver-y += i82801er_ide.o
-driver-y += i82801er_sata.o
-driver-y += i82801er_ehci.o
-driver-y += i82801er_smbus.o
-driver-y += i82801er_pci.o
-driver-y += i82801er_ac97.o
-obj-y += i82801er_watchdog.o
-obj-y += i82801er_reset.o
diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig
new file mode 100644
index 0000000..905af26
--- /dev/null
+++ b/src/southbridge/intel/i82801ex/Kconfig
@@ -0,0 +1,3 @@
+config SOUTHBRIDGE_INTEL_I82801EX
+ bool
+ select IOAPIC
diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc
new file mode 100644
index 0000000..66a217b
--- /dev/null
+++ b/src/southbridge/intel/i82801ex/Makefile.inc
@@ -0,0 +1,11 @@
+driver-y += i82801ex.o
+driver-y += i82801ex_uhci.o
+driver-y += i82801ex_lpc.o
+driver-y += i82801ex_ide.o
+driver-y += i82801ex_sata.o
+driver-y += i82801ex_ehci.o
+driver-y += i82801ex_smbus.o
+driver-y += i82801ex_pci.o
+driver-y += i82801ex_ac97.o
+obj-y += i82801ex_watchdog.o
+obj-y += i82801ex_reset.o
diff --git a/src/southbridge/intel/i82801er/chip.h b/src/southbridge/intel/i82801ex/chip.h
similarity index 80%
rename from src/southbridge/intel/i82801er/chip.h
rename to src/southbridge/intel/i82801ex/chip.h
index eb63889..34a0a97 100644
--- a/src/southbridge/intel/i82801er/chip.h
+++ b/src/southbridge/intel/i82801ex/chip.h
@@ -1,7 +1,7 @@
-#ifndef I82801ER_CHIP_H
-#define I82801ER_CHIP_H
+#ifndef I82801EX_CHIP_H
+#define I82801EX_CHIP_H
-struct southbridge_intel_i82801er_config
+struct southbridge_intel_i82801ex_config
{
#define ICH5R_GPIO_USE_MASK 0x03
@@ -30,7 +30,7 @@
unsigned int pirq_a_d;
unsigned int pirq_e_h;
};
-extern struct chip_operations southbridge_intel_i82801er_ops;
+extern struct chip_operations southbridge_intel_i82801ex_ops;
-#endif /* I82801ER_CHIP_H */
+#endif /* I82801EX_CHIP_H */
diff --git a/src/southbridge/intel/i82801er/cmos_failover.c b/src/southbridge/intel/i82801ex/cmos_failover.c
similarity index 100%
rename from src/southbridge/intel/i82801er/cmos_failover.c
rename to src/southbridge/intel/i82801ex/cmos_failover.c
diff --git a/src/southbridge/intel/i82801er/i82801er.c b/src/southbridge/intel/i82801ex/i82801ex.c
similarity index 78%
rename from src/southbridge/intel/i82801er/i82801er.c
rename to src/southbridge/intel/i82801ex/i82801ex.c
index 19b0666..bc5f04b 100644
--- a/src/southbridge/intel/i82801er/i82801er.c
+++ b/src/southbridge/intel/i82801ex/i82801ex.c
@@ -2,15 +2,15 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "i82801er.h"
+#include "i82801ex.h"
-void i82801er_enable(device_t dev)
+void i82801ex_enable(device_t dev)
{
device_t lpc_dev;
unsigned index = 0;
uint16_t reg_old, reg;
- /* See if we are behind the i82801er pci bridge */
+ /* See if we are behind the i82801ex pci bridge */
lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
if((dev->path.pci.devfn &0xf8)== 0xf8) {
index = dev->path.pci.devfn & 7;
@@ -42,7 +42,7 @@
}
-struct chip_operations southbridge_intel_i82801er_ops = {
- CHIP_NAME("Intel 82801ER Southbridge")
- .enable_dev = i82801er_enable,
+struct chip_operations southbridge_intel_i82801ex_ops = {
+ CHIP_NAME("Intel ICH5 (82801Ex) Series Southbridge")
+ .enable_dev = i82801ex_enable,
};
diff --git a/src/southbridge/intel/i82801er/i82801er.h b/src/southbridge/intel/i82801ex/i82801ex.h
similarity index 64%
rename from src/southbridge/intel/i82801er/i82801er.h
rename to src/southbridge/intel/i82801ex/i82801ex.h
index bd74101..67fecdd 100644
--- a/src/southbridge/intel/i82801er/i82801er.h
+++ b/src/southbridge/intel/i82801ex/i82801ex.h
@@ -1,9 +1,9 @@
-#ifndef I82801ER_H
-#define I82801ER_H
+#ifndef I82801EX_H
+#define I82801EX_H
#include "chip.h"
-extern void i82801er_enable(device_t dev);
+extern void i82801ex_enable(device_t dev);
#define PCI_DMA_CFG 0x90
#define SERIRQ_CNTL 0x64
@@ -12,4 +12,4 @@
#define RTC_CONF 0xd8
#define GEN_PMCON_3 0xa4
-#endif /* I82801ER_H */
+#endif /* I82801EX_H */
diff --git a/src/southbridge/intel/i82801er/i82801er_ac97.c b/src/southbridge/intel/i82801ex/i82801ex_ac97.c
similarity index 94%
rename from src/southbridge/intel/i82801er/i82801er_ac97.c
rename to src/southbridge/intel/i82801ex/i82801ex_ac97.c
index 0525a5e..65502dd 100644
--- a/src/southbridge/intel/i82801er/i82801er_ac97.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_ac97.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801er.h"
+#include "i82801ex.h"
static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
@@ -21,7 +21,7 @@
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
- .enable = i82801er_enable,
+ .enable = i82801ex_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/intel/i82801er/i82801er_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
similarity index 98%
rename from src/southbridge/intel/i82801er/i82801er_early_smbus.c
rename to src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
index 42a5568..c86bf23 100644
--- a/src/southbridge/intel/i82801er/i82801er_early_smbus.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
@@ -1,4 +1,4 @@
-#include "i82801er_smbus.h"
+#include "i82801ex_smbus.h"
#define SMBUS_IO_BASE 0x0f00
diff --git a/src/southbridge/intel/i82801er/i82801er_ehci.c b/src/southbridge/intel/i82801ex/i82801ex_ehci.c
similarity index 95%
rename from src/southbridge/intel/i82801er/i82801er_ehci.c
rename to src/southbridge/intel/i82801ex/i82801ex_ehci.c
index 47b18de..60b1f30 100644
--- a/src/southbridge/intel/i82801er/i82801er_ehci.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_ehci.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801er.h"
+#include "i82801ex.h"
static void ehci_init(struct device *dev)
{
@@ -39,7 +39,7 @@
.enable_resources = pci_dev_enable_resources,
.init = ehci_init,
.scan_bus = 0,
- .enable = i82801er_enable,
+ .enable = i82801ex_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/intel/i82801er/i82801er_ide.c b/src/southbridge/intel/i82801ex/i82801ex_ide.c
similarity index 89%
rename from src/southbridge/intel/i82801er/i82801er_ide.c
rename to src/southbridge/intel/i82801ex/i82801ex_ide.c
index 8d8e391..b4d2311 100644
--- a/src/southbridge/intel/i82801er/i82801er_ide.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_ide.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801er.h"
+#include "i82801ex.h"
static void ide_init(struct device *dev)
{
@@ -16,7 +16,7 @@
printk_debug("IDE Enabled\n");
}
-static void i82801er_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* This value is also visible in uchi[0-2] and smbus functions */
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -24,7 +24,7 @@
}
static struct pci_operations lops_pci = {
- .set_subsystem = i82801er_ide_set_subsystem,
+ .set_subsystem = i82801ex_ide_set_subsystem,
};
static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources,
diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
similarity index 87%
rename from src/southbridge/intel/i82801er/i82801er_lpc.c
rename to src/southbridge/intel/i82801ex/i82801ex_lpc.c
index 357e181..6cf8124 100644
--- a/src/southbridge/intel/i82801er/i82801er_lpc.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
@@ -10,7 +10,7 @@
#include <pc80/isa-dma.h>
#include <arch/io.h>
#include <arch/ioapic.h>
-#include "i82801er.h"
+#include "i82801ex.h"
#define ACPI_BAR 0x40
#define GPIO_BAR 0x58
@@ -24,7 +24,7 @@
#endif
#define SERIRQ_CNTL 0x64
-static void i82801er_enable_serial_irqs(device_t dev)
+static void i82801ex_enable_serial_irqs(device_t dev)
{
/* set packet length and toggle silent mode bit */
pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
@@ -32,22 +32,22 @@
}
#define PCI_DMA_CFG 0x90
-static void i82801er_pci_dma_cfg(device_t dev)
+static void i82801ex_pci_dma_cfg(device_t dev)
{
/* Set PCI DMA CFG to lpc I/F DMA */
pci_write_config16(dev, PCI_DMA_CFG, 0xfcff);
}
#define LPC_EN 0xe6
-static void i82801er_enable_lpc(device_t dev)
+static void i82801ex_enable_lpc(device_t dev)
{
/* lpc i/f enable */
pci_write_config8(dev, LPC_EN, 0x0d);
}
-typedef struct southbridge_intel_i82801er_config config_t;
+typedef struct southbridge_intel_i82801ex_config config_t;
-static void set_i82801er_gpio_use_sel(
+static void set_i82801ex_gpio_use_sel(
device_t dev, struct resource *res, config_t *config)
{
uint32_t gpio_use_sel, gpio_use_sel2;
@@ -76,7 +76,7 @@
outl(gpio_use_sel2, res->base + 0x30);
}
-static void set_i82801er_gpio_direction(
+static void set_i82801ex_gpio_direction(
device_t dev, struct resource *res, config_t *config)
{
uint32_t gpio_io_sel, gpio_io_sel2;
@@ -105,7 +105,7 @@
outl(gpio_io_sel2, res->base + 0x34);
}
-static void set_i82801er_gpio_level(
+static void set_i82801ex_gpio_level(
device_t dev, struct resource *res, config_t *config)
{
uint32_t gpio_lvl, gpio_lvl2;
@@ -140,7 +140,7 @@
outl(gpio_lvl2, res->base + 0x38);
}
-static void set_i82801er_gpio_inv(
+static void set_i82801ex_gpio_inv(
device_t dev, struct resource *res, config_t *config)
{
uint32_t gpio_inv;
@@ -161,7 +161,7 @@
outl(gpio_inv, res->base + 0x2c);
}
-static void i82801er_pirq_init(device_t dev)
+static void i82801ex_pirq_init(device_t dev)
{
config_t *config;
@@ -177,7 +177,7 @@
}
-static void i82801er_gpio_init(device_t dev)
+static void i82801ex_gpio_init(device_t dev)
{
struct resource *res;
config_t *config;
@@ -199,16 +199,16 @@
}
/* Set the use selects */
- set_i82801er_gpio_use_sel(dev, res, config);
+ set_i82801ex_gpio_use_sel(dev, res, config);
/* Set the IO direction */
- set_i82801er_gpio_direction(dev, res, config);
+ set_i82801ex_gpio_direction(dev, res, config);
/* Setup the input inverters */
- set_i82801er_gpio_inv(dev, res, config);
+ set_i82801ex_gpio_inv(dev, res, config);
/* Set the value on the GPIO output pins */
- set_i82801er_gpio_level(dev, res, config);
+ set_i82801ex_gpio_level(dev, res, config);
}
@@ -250,11 +250,11 @@
pci_write_config32(dev, 0xd4, value);
setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
- i82801er_enable_serial_irqs(dev);
+ i82801ex_enable_serial_irqs(dev);
- i82801er_pci_dma_cfg(dev);
+ i82801ex_pci_dma_cfg(dev);
- i82801er_enable_lpc(dev);
+ i82801ex_enable_lpc(dev);
/* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00);
@@ -269,10 +269,10 @@
printk_info("set power %s after power fail\n", pwr_on?"on":"off");
/* Set up the PIRQ */
- i82801er_pirq_init(dev);
+ i82801ex_pirq_init(dev);
/* Set the state of the gpio lines */
- i82801er_gpio_init(dev);
+ i82801ex_gpio_init(dev);
/* Initialize the real time clock */
rtc_init(0);
@@ -286,7 +286,7 @@
enable_hpet(dev);
}
-static void i82801er_lpc_read_resources(device_t dev)
+static void i82801ex_lpc_read_resources(device_t dev)
{
struct resource *res;
@@ -318,7 +318,7 @@
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void i82801er_lpc_enable_resources(device_t dev)
+static void i82801ex_lpc_enable_resources(device_t dev)
{
uint8_t acpi_cntl, gpio_cntl;
@@ -343,12 +343,12 @@
};
static struct device_operations lpc_ops = {
- .read_resources = i82801er_lpc_read_resources,
+ .read_resources = i82801ex_lpc_read_resources,
.set_resources = pci_dev_set_resources,
- .enable_resources = i82801er_lpc_enable_resources,
+ .enable_resources = i82801ex_lpc_enable_resources,
.init = lpc_init,
.scan_bus = scan_static_bus,
- .enable = i82801er_enable,
+ .enable = i82801ex_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/intel/i82801er/i82801er_pci.c b/src/southbridge/intel/i82801ex/i82801ex_pci.c
similarity index 97%
rename from src/southbridge/intel/i82801er/i82801er_pci.c
rename to src/southbridge/intel/i82801ex/i82801ex_pci.c
index 6aa578f..650628b 100644
--- a/src/southbridge/intel/i82801er/i82801er_pci.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_pci.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801er.h"
+#include "i82801ex.h"
static void pci_init(struct device *dev)
{
diff --git a/src/southbridge/intel/i82801er/i82801er_reset.c b/src/southbridge/intel/i82801ex/i82801ex_reset.c
similarity index 78%
rename from src/southbridge/intel/i82801er/i82801er_reset.c
rename to src/southbridge/intel/i82801ex/i82801ex_reset.c
index fa41756..a1d92a7 100644
--- a/src/southbridge/intel/i82801er/i82801er_reset.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_reset.c
@@ -1,6 +1,6 @@
#include <arch/io.h>
-void i82801er_hard_reset(void)
+void i82801ex_hard_reset(void)
{
/* Try rebooting through port 0xcf9 */
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
diff --git a/src/southbridge/intel/i82801er/i82801er_sata.c b/src/southbridge/intel/i82801ex/i82801ex_sata.c
similarity index 98%
rename from src/southbridge/intel/i82801er/i82801er_sata.c
rename to src/southbridge/intel/i82801ex/i82801ex_sata.c
index c710d83..98431ed 100644
--- a/src/southbridge/intel/i82801er/i82801er_sata.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_sata.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801er.h"
+#include "i82801ex.h"
static void sata_init(struct device *dev)
{
diff --git a/src/southbridge/intel/i82801er/i82801er_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_smbus.c
similarity index 92%
rename from src/southbridge/intel/i82801er/i82801er_smbus.c
rename to src/southbridge/intel/i82801ex/i82801ex_smbus.c
index ee32c69..adfbcb7c 100644
--- a/src/southbridge/intel/i82801er/i82801er_smbus.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_smbus.c
@@ -5,8 +5,8 @@
#include <device/pci_ops.h>
#include <device/smbus.h>
#include <arch/io.h>
-#include "i82801er.h"
-#include "i82801er_smbus.h"
+#include "i82801ex.h"
+#include "i82801ex_smbus.h"
static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
{
@@ -32,7 +32,7 @@
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = scan_static_bus,
- .enable = i82801er_enable,
+ .enable = i82801ex_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
diff --git a/src/southbridge/intel/i82801er/i82801er_smbus.h b/src/southbridge/intel/i82801ex/i82801ex_smbus.h
similarity index 100%
rename from src/southbridge/intel/i82801er/i82801er_smbus.h
rename to src/southbridge/intel/i82801ex/i82801ex_smbus.h
diff --git a/src/southbridge/intel/i82801er/i82801er_uhci.c b/src/southbridge/intel/i82801ex/i82801ex_uhci.c
similarity index 95%
rename from src/southbridge/intel/i82801er/i82801er_uhci.c
rename to src/southbridge/intel/i82801ex/i82801ex_uhci.c
index c0f4231..177b820 100644
--- a/src/southbridge/intel/i82801er/i82801er_uhci.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_uhci.c
@@ -3,7 +3,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "i82801er.h"
+#include "i82801ex.h"
static void uhci_init(struct device *dev)
{
@@ -32,7 +32,7 @@
.enable_resources = pci_dev_enable_resources,
.init = uhci_init,
.scan_bus = 0,
- .enable = i82801er_enable,
+ .enable = i82801ex_enable,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/intel/i82801er/i82801er_watchdog.c b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c
similarity index 100%
rename from src/southbridge/intel/i82801er/i82801er_watchdog.c
rename to src/southbridge/intel/i82801ex/i82801ex_watchdog.c