soc/amd/*/i2c: Move reset_i2c_peripherals to i2c.c
Move i2c SoC related code from early_fch.c to i2c.c
TEST=build boards for each SoC
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I69d4b32cf95ce74586bd8971c7ee4b56c1c2fc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 3addcf8..4935f66 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -12,13 +12,6 @@
#include "chip.h"
-/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
-static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
- I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
- I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
- I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
- I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
-};
static void lpc_configure_decodes(void)
{
@@ -26,17 +19,6 @@
lpc_enable_port80();
}
-static void reset_i2c_peripherals(void)
-{
- const struct soc_amd_cezanne_config *cfg = config_of_soc();
- struct soc_i2c_peripheral_reset_info reset_info;
-
- reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
- reset_info.i2c_scl = i2c_scl_pins;
- reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
- sb_reset_i2c_peripherals(&reset_info);
-}
-
/* Before console init */
void fch_pre_init(void)
{
diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c
index ae49a06..98e2413 100644
--- a/src/soc/amd/cezanne/i2c.c
+++ b/src/soc/amd/cezanne/i2c.c
@@ -6,6 +6,14 @@
#include <soc/southbridge.h>
#include "chip.h"
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
+static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
+ I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
+ I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
+ I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
+ I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
+};
+
#if ENV_X86
static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
{ I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" },
@@ -32,6 +40,17 @@
}
#endif
+void reset_i2c_peripherals(void)
+{
+ const struct soc_amd_cezanne_config *cfg = config_of_soc();
+ struct soc_i2c_peripheral_reset_info reset_info;
+
+ reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+ reset_info.i2c_scl = i2c_scl_pins;
+ reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
+ sb_reset_i2c_peripherals(&reset_info);
+}
+
void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
{
const struct soc_amd_cezanne_config *config = config_of_soc();
diff --git a/src/soc/amd/cezanne/include/soc/i2c.h b/src/soc/amd/cezanne/include/soc/i2c.h
index dba16db..c0e3e80 100644
--- a/src/soc/amd/cezanne/include/soc/i2c.h
+++ b/src/soc/amd/cezanne/include/soc/i2c.h
@@ -24,5 +24,6 @@
#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
void i2c_set_bar(unsigned int bus, uintptr_t bar);
+void reset_i2c_peripherals(void);
#endif /* AMD_CEZANNE_I2C_H */
diff --git a/src/soc/amd/mendocino/early_fch.c b/src/soc/amd/mendocino/early_fch.c
index d37b45d..3331737 100644
--- a/src/soc/amd/mendocino/early_fch.c
+++ b/src/soc/amd/mendocino/early_fch.c
@@ -14,25 +14,6 @@
#include "chip.h"
-/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
-static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
- I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
- I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
- I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
- I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
-};
-
-static void reset_i2c_peripherals(void)
-{
- const struct soc_amd_mendocino_config *cfg = config_of_soc();
- struct soc_i2c_peripheral_reset_info reset_info;
-
- reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
- reset_info.i2c_scl = i2c_scl_pins;
- reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
- sb_reset_i2c_peripherals(&reset_info);
-}
-
/* Before console init */
void fch_pre_init(void)
{
diff --git a/src/soc/amd/mendocino/i2c.c b/src/soc/amd/mendocino/i2c.c
index 06c60ab..75efe0c 100644
--- a/src/soc/amd/mendocino/i2c.c
+++ b/src/soc/amd/mendocino/i2c.c
@@ -6,6 +6,14 @@
#include <soc/southbridge.h>
#include "chip.h"
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
+static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
+ I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
+ I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
+ I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
+ I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
+};
+
#if ENV_X86
static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
{ I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" },
@@ -32,6 +40,17 @@
}
#endif
+void reset_i2c_peripherals(void)
+{
+ const struct soc_amd_mendocino_config *cfg = config_of_soc();
+ struct soc_i2c_peripheral_reset_info reset_info;
+
+ reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+ reset_info.i2c_scl = i2c_scl_pins;
+ reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
+ sb_reset_i2c_peripherals(&reset_info);
+}
+
void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
{
const struct soc_amd_mendocino_config *config = config_of_soc();
diff --git a/src/soc/amd/mendocino/include/soc/i2c.h b/src/soc/amd/mendocino/include/soc/i2c.h
index d06a92d..157ac86 100644
--- a/src/soc/amd/mendocino/include/soc/i2c.h
+++ b/src/soc/amd/mendocino/include/soc/i2c.h
@@ -24,5 +24,6 @@
#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
void i2c_set_bar(unsigned int bus, uintptr_t bar);
+void reset_i2c_peripherals(void);
#endif /* AMD_MENDOCINO_I2C_H */
diff --git a/src/soc/amd/morgana/early_fch.c b/src/soc/amd/morgana/early_fch.c
index f6ccf55..1ec7105 100644
--- a/src/soc/amd/morgana/early_fch.c
+++ b/src/soc/amd/morgana/early_fch.c
@@ -14,25 +14,6 @@
#include "chip.h"
-/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
-static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
- I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
- I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
- I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
- I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
-};
-
-static void reset_i2c_peripherals(void)
-{
- const struct soc_amd_morgana_config *cfg = config_of_soc();
- struct soc_i2c_peripheral_reset_info reset_info;
-
- reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
- reset_info.i2c_scl = i2c_scl_pins;
- reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
- sb_reset_i2c_peripherals(&reset_info);
-}
-
/* Before console init */
void fch_pre_init(void)
{
diff --git a/src/soc/amd/morgana/i2c.c b/src/soc/amd/morgana/i2c.c
index 23a38ba..13b3959 100644
--- a/src/soc/amd/morgana/i2c.c
+++ b/src/soc/amd/morgana/i2c.c
@@ -8,6 +8,14 @@
#include <soc/southbridge.h>
#include "chip.h"
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
+static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
+ I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
+ I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
+ I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
+ I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
+};
+
#if ENV_X86
static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
{ I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" },
@@ -34,6 +42,17 @@
}
#endif
+void reset_i2c_peripherals(void)
+{
+ const struct soc_amd_morgana_config *cfg = config_of_soc();
+ struct soc_i2c_peripheral_reset_info reset_info;
+
+ reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+ reset_info.i2c_scl = i2c_scl_pins;
+ reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
+ sb_reset_i2c_peripherals(&reset_info);
+}
+
void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
{
const struct soc_amd_morgana_config *config = config_of_soc();
diff --git a/src/soc/amd/morgana/include/soc/i2c.h b/src/soc/amd/morgana/include/soc/i2c.h
index 10b7249..900bdca 100644
--- a/src/soc/amd/morgana/include/soc/i2c.h
+++ b/src/soc/amd/morgana/include/soc/i2c.h
@@ -26,5 +26,6 @@
#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
void i2c_set_bar(unsigned int bus, uintptr_t bar);
+void reset_i2c_peripherals(void);
#endif /* AMD_MORGANA_I2C_H */
diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c
index d0c10f2..f5d392c 100644
--- a/src/soc/amd/picasso/early_fch.c
+++ b/src/soc/amd/picasso/early_fch.c
@@ -14,30 +14,12 @@
#include "chip.h"
-/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
-static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
- I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
- I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
- /* I2C4 is a peripheral device only */
-};
-
static void lpc_configure_decodes(void)
{
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
lpc_enable_port80();
}
-static void reset_i2c_peripherals(void)
-{
- const struct soc_amd_picasso_config *cfg = config_of_soc();
- struct soc_i2c_peripheral_reset_info reset_info;
-
- reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
- reset_info.i2c_scl = i2c_scl_pins;
- reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
- sb_reset_i2c_peripherals(&reset_info);
-}
-
/* Before console init */
void fch_pre_init(void)
{
diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c
index afbc8bd..d718436 100644
--- a/src/soc/amd/picasso/i2c.c
+++ b/src/soc/amd/picasso/i2c.c
@@ -9,6 +9,13 @@
#include <soc/southbridge.h>
#include "chip.h"
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
+static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
+ I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
+ I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
+ /* I2C4 is a peripheral device only */
+};
+
#if ENV_X86
/* Preferably keep all the I2C controllers operating in a specific mode together. */
static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
@@ -38,6 +45,17 @@
}
#endif
+void reset_i2c_peripherals(void)
+{
+ const struct soc_amd_picasso_config *cfg = config_of_soc();
+ struct soc_i2c_peripheral_reset_info reset_info;
+
+ reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+ reset_info.i2c_scl = i2c_scl_pins;
+ reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
+ sb_reset_i2c_peripherals(&reset_info);
+}
+
void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
{
/* TODO: Picasso supports I2C RX pad configurations 3.3V, 1.8V and off, so make this
diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h
index f62cb11..7056272 100644
--- a/src/soc/amd/picasso/include/soc/i2c.h
+++ b/src/soc/amd/picasso/include/soc/i2c.h
@@ -25,5 +25,6 @@
/* Sets the base address for the specific I2C bus. */
void i2c_set_bar(unsigned int bus, uintptr_t bar);
+void reset_i2c_peripherals(void);
#endif /* AMD_PICASSO_I2C_H */
diff --git a/src/soc/amd/stoneyridge/early_fch.c b/src/soc/amd/stoneyridge/early_fch.c
index 5a8de13..b46bde7 100644
--- a/src/soc/amd/stoneyridge/early_fch.c
+++ b/src/soc/amd/stoneyridge/early_fch.c
@@ -12,14 +12,6 @@
#include "chip.h"
-/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
-static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
- I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
- I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
- I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
- I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
-};
-
static void sb_lpc_decode(void)
{
u32 tmp = 0;
@@ -111,17 +103,6 @@
}
}
-static void reset_i2c_peripherals(void)
-{
- const struct soc_amd_stoneyridge_config *cfg = config_of_soc();
- struct soc_i2c_peripheral_reset_info reset_info;
-
- reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
- reset_info.i2c_scl = i2c_scl_pins;
- reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
- sb_reset_i2c_peripherals(&reset_info);
-}
-
/* Before console init */
void bootblock_fch_early_init(void)
{
diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c
index e589b04..f7adbec 100644
--- a/src/soc/amd/stoneyridge/i2c.c
+++ b/src/soc/amd/stoneyridge/i2c.c
@@ -7,6 +7,14 @@
#include "chip.h"
#include <drivers/i2c/designware/dw_i2c.h>
+/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
+static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
+ I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
+ I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
+ I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
+ I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
+};
+
static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = {
{ I2C_MASTER_MODE, APU_I2C0_BASE, "I2CA" },
{ I2C_MASTER_MODE, APU_I2C1_BASE, "I2CB" },
@@ -14,6 +22,17 @@
{ I2C_MASTER_MODE, APU_I2C3_BASE, "I2CD" },
};
+void reset_i2c_peripherals(void)
+{
+ const struct soc_amd_stoneyridge_config *cfg = config_of_soc();
+ struct soc_i2c_peripheral_reset_info reset_info;
+
+ reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
+ reset_info.i2c_scl = i2c_scl_pins;
+ reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
+ sb_reset_i2c_peripherals(&reset_info);
+}
+
const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
{
*num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h
index b16084b..505802e 100644
--- a/src/soc/amd/stoneyridge/include/soc/i2c.h
+++ b/src/soc/amd/stoneyridge/include/soc/i2c.h
@@ -22,4 +22,6 @@
#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx
#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
+void reset_i2c_peripherals(void);
+
#endif /* AMD_STONEYRIDGE_I2C_H */