diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index 32a1428..af9a8bf 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -12,7 +12,7 @@
 static inline void print_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
+	for (dev = PCI_DEV(0, 0, 0);
 		dev <= PCI_DEV(0xff, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
@@ -32,7 +32,7 @@
 	int i;
 	print_debug_pci_dev(dev);
 
-	for(i = 0; i < 256; i++) {
+	for (i = 0; i < 256; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0)
                         printk(BIOS_DEBUG, "\n%02x:",i);
@@ -45,7 +45,7 @@
 static inline void dump_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
+	for (dev = PCI_DEV(0, 0, 0);
 		dev <= PCI_DEV(0xff, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
@@ -62,7 +62,7 @@
 static inline void dump_pci_devices_on_bus(unsigned busn)
 {
         device_t dev;
-        for(dev = PCI_DEV(busn, 0, 0);
+        for (dev = PCI_DEV(busn, 0, 0);
                 dev <= PCI_DEV(busn, 0x1f, 0x7);
                 dev += PCI_DEV(0,0,1)) {
                 uint32_t id;
@@ -80,13 +80,13 @@
 {
 	int i;
 	printk(BIOS_DEBUG, "\n");
-	for(i = 0; i < 4; i++) {
+	for (i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
 		if (device) {
 			int j;
 			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-			for(j = 0; j < 128; j++) {
+			for (j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0)
@@ -104,7 +104,7 @@
 		if (device) {
 			int j;
                         printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
-			for(j = 0; j < 128; j++) {
+			for (j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0)
@@ -124,11 +124,11 @@
 {
 	unsigned device;
         printk(BIOS_DEBUG, "\n");
-        for(device = 1; device < 0x80; device++) {
+        for (device = 1; device < 0x80; device++) {
                 int j;
-		if( smbus_read_byte(device, 0) < 0 ) continue;
+		if ( smbus_read_byte(device, 0) < 0 ) continue;
 		printk(BIOS_DEBUG, "smbus: %02x", device);
-                for(j = 0; j < 256; j++) {
+                for (j = 0; j < 256; j++) {
                 	int status;
                         unsigned char byte;
                         status = smbus_read_byte(device, j);
@@ -149,7 +149,7 @@
 
 	int i;
 	printk(BIOS_DEBUG, "%04x:\n", port);
-        for(i=0;i<256;i++) {
+        for (i=0;i<256;i++) {
                 uint8_t val;
                 if ((i & 0x0f) == 0)
 			printk(BIOS_DEBUG, "%02x:", i);
@@ -166,8 +166,8 @@
 {
         unsigned i;
 	printk(BIOS_DEBUG, "dump_mem:");
-        for(i=start;i<end;i++) {
-		if((i & 0xf)==0)
+        for (i=start;i<end;i++) {
+		if ((i & 0xf)==0)
 			printk(BIOS_DEBUG, "\n%08x:", i);
 		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
         }
diff --git a/src/northbridge/intel/e7501/reset_test.c b/src/northbridge/intel/e7501/reset_test.c
index 1c0dad5..62e3283 100644
--- a/src/northbridge/intel/e7501/reset_test.c
+++ b/src/northbridge/intel/e7501/reset_test.c
@@ -10,7 +10,7 @@
 
 	dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
 
-	if( (dword & DRC_DONE) != 0 ) {
+	if ( (dword & DRC_DONE) != 0 ) {
 		return 1;
 	}
 
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index cdf6e7e..33f1ed1 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -22,7 +22,7 @@
 void print_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
+	for (dev = PCI_DEV(0, 0, 0);
 		dev <= PCI_DEV(0xff, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
@@ -42,7 +42,7 @@
 	int i;
 	print_debug_pci_dev(dev);
 
-	for(i = 0; i < 256; i++) {
+	for (i = 0; i < 256; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0)
                         printk(BIOS_DEBUG, "\n%02x:",i);
@@ -55,7 +55,7 @@
 void dump_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
+	for (dev = PCI_DEV(0, 0, 0);
 		dev <= PCI_DEV(0xff, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
@@ -72,7 +72,7 @@
 void dump_pci_devices_on_bus(unsigned busn)
 {
         device_t dev;
-        for(dev = PCI_DEV(busn, 0, 0);
+        for (dev = PCI_DEV(busn, 0, 0);
                 dev <= PCI_DEV(busn, 0x1f, 0x7);
                 dev += PCI_DEV(0,0,1)) {
                 uint32_t id;
@@ -90,13 +90,13 @@
 {
 	int i;
 	printk(BIOS_DEBUG, "\n");
-	for(i = 0; i < 4; i++) {
+	for (i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
 		if (device) {
 			int j;
 			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-			for(j = 0; j < 128; j++) {
+			for (j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0)
@@ -114,7 +114,7 @@
 		if (device) {
 			int j;
                         printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
-			for(j = 0; j < 128; j++) {
+			for (j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0)
@@ -134,11 +134,11 @@
 {
 	unsigned device;
         printk(BIOS_DEBUG, "\n");
-        for(device = 1; device < 0x80; device++) {
+        for (device = 1; device < 0x80; device++) {
                 int j;
-		if( spd_read_byte(device, 0) < 0 ) continue;
+		if ( spd_read_byte(device, 0) < 0 ) continue;
 		printk(BIOS_DEBUG, "smbus: %02x", device);
-                for(j = 0; j < 256; j++) {
+                for (j = 0; j < 256; j++) {
                 	int status;
                         unsigned char byte;
                         status = spd_read_byte(device, j);
@@ -159,7 +159,7 @@
 
 	int i;
 	printk(BIOS_DEBUG, "%04x:\n", port);
-        for(i=0;i<256;i++) {
+        for (i=0;i<256;i++) {
                 uint8_t val;
                 if ((i & 0x0f) == 0)
 			printk(BIOS_DEBUG, "%02x:", i);
@@ -176,8 +176,8 @@
 {
         unsigned i;
 	printk(BIOS_DEBUG, "dump_mem:");
-        for(i=start;i<end;i++) {
-		if((i & 0xf)==0)
+        for (i=start;i<end;i++) {
+		if ((i & 0xf)==0)
 			printk(BIOS_DEBUG, "\n%08x:", i);
 		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
         }
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 7734ca5..259fdd2 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -1710,7 +1710,7 @@
 	/* And for good luck 6 more CBRs */
 	RAM_DEBUG_MESSAGE("Ram Enable 8\n");
 	int i;
-	for(i=0; i<8; i++)
+	for (i=0; i<8; i++)
 		do_ram_command(RAM_COMMAND_CBR, 0);
 
 	/* 9 mode register set */
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
index 1cc1bc0..2ac1a23 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -63,38 +63,38 @@
 	config = dev->chip_info;
 
 	/* Set SPD addresses */
-	if(config->SpdBaseAddress_0_0) {
+	if (config->SpdBaseAddress_0_0) {
 		UpdData->PcdSpdBaseAddress_0_0 = config->SpdBaseAddress_0_0;
 	}
-	if(config->SpdBaseAddress_0_1) {
+	if (config->SpdBaseAddress_0_1) {
 		UpdData->PcdSpdBaseAddress_0_1 = config->SpdBaseAddress_0_1;
 	}
-	if(config->SpdBaseAddress_1_0) {
+	if (config->SpdBaseAddress_1_0) {
 		UpdData->PcdSpdBaseAddress_1_0 = config->SpdBaseAddress_1_0;
 	}
-	if(config->SpdBaseAddress_1_1) {
+	if (config->SpdBaseAddress_1_1) {
 		UpdData->PcdSpdBaseAddress_1_1 = config->SpdBaseAddress_1_1;
 	}
-	if(config->EccSupport) {
+	if (config->EccSupport) {
 		UpdData->PcdEccSupport = config->EccSupport;
 	}
-	if(config->PrintDebugMessages) {
+	if (config->PrintDebugMessages) {
 		UpdData->PcdPrintDebugMessages = config->PrintDebugMessages;
 	}
-	if(config->Bifurcation) {
+	if (config->Bifurcation) {
 		UpdData->PcdBifurcation = config->Bifurcation;
 	}
-	if(config->MemoryDown) {
+	if (config->MemoryDown) {
 		UpdData->PcdMemoryDown = config->MemoryDown;
 	}
 
 	UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20;
 
-	if(config->MrcRmtCpgcExpLoopCntValue) {
+	if (config->MrcRmtCpgcExpLoopCntValue) {
 		UpdData->PcdMrcRmtCpgcExpLoopCntValue =
 				config->MrcRmtCpgcExpLoopCntValue;
 	}
-	if(config->MrcRmtCpgcNumBursts) {
+	if (config->MrcRmtCpgcNumBursts) {
 		UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts;
 	}
 #if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT)
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 20779e7..ea0bc54 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -149,7 +149,7 @@
 {
 	int i;
 
-	for(i = start; i < end; i++){
+	for (i = start; i < end; i++){
 		u64 physical_address = base + i*inc;
 		/* swizzle the 32:39 bits to 4:11 */
 		u32 word = physical_address | ((physical_address >> 28) & 0xff0) | 1;
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index 8d37f38..c8e3221 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -46,7 +46,7 @@
 	printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
 #endif
 	/* FIXME Me temporary hack */
-	if(pci_tolm > 0xe0000000)
+	if (pci_tolm > 0xe0000000)
 		pci_tolm = 0xe0000000;
 	/* Ensure pci_tolm is 128M aligned */
 	pci_tolm &= 0xf8000000;
diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c
index 6ca7cfd..71a2bf2 100644
--- a/src/northbridge/intel/i3100/pciexp_porta.c
+++ b/src/northbridge/intel/i3100/pciexp_porta.c
@@ -35,7 +35,7 @@
 	/* Get the chip configuration */
 	config = dev->chip_info;
 
-	if(config->intrline) {
+	if (config->intrline) {
 		pci_write_config32(dev, 0x3c, config->intrline);
 	}
 
diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
index 2cc7bb1..b5e35d6 100644
--- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
+++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
@@ -36,7 +36,7 @@
 	/* Get the chip configuration */
 	config = dev->chip_info;
 
-	if(config->intrline) {
+	if (config->intrline) {
 		pci_write_config32(dev, 0x3c, config->intrline);
 	}
 
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 443716f..39e40e0 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -63,7 +63,7 @@
 	int max;
 
 	max = ARRAY_SIZE(register_values);
-	for(i = 0; i < max; i += 3) {
+	for (i = 0; i < max; i += 3) {
 		device_t dev;
 		u32 where;
 		u32 reg;
@@ -162,7 +162,7 @@
 	int i;
 	int cum;
 
-	for(i = cum = 0; i < DIMM_SOCKETS; i++) {
+	for (i = cum = 0; i < DIMM_SOCKETS; i++) {
 		struct dimm_size sz;
 		if (dimm_mask & (1 << i)) {
 			sz = spd_get_dimm_size(ctrl->channel0[i]);
@@ -174,7 +174,7 @@
 			cum += (1 << sz.side1);
 			/* DRB = 0x60 */
 			pci_write_config8(ctrl->f0, DRB + (i*2), cum);
-			if( sz.side2 > 28) {
+			if ( sz.side2 > 28) {
 				sz.side2 -= 29;
 				cum += (1 << sz.side2);
 			}
@@ -189,7 +189,7 @@
 	/* set TOM top of memory 0xcc */
 	pci_write_config16(ctrl->f0, TOM, cum);
 	/* set TOLM top of low memory */
-	if(cum > 0x18) {
+	if (cum > 0x18) {
 		cum = 0x18;
 	}
 	cum <<= 11;
@@ -204,7 +204,7 @@
 	u32 dimm_mask;
 	int i;
 	dimm_mask = 0;
-	for(i = 0; i < DIMM_SOCKETS; i++) {
+	for (i = 0; i < DIMM_SOCKETS; i++) {
 		int byte;
 		u16 device;
 		device = ctrl->channel0[i];
@@ -235,7 +235,7 @@
 	int cnt;
 
 	dra = 0;
-	for(cnt=0; cnt < 4; cnt++) {
+	for (cnt=0; cnt < 4; cnt++) {
 		if (!(dimm_mask & (1 << cnt))) {
 			continue;
 		}
@@ -260,7 +260,7 @@
 		if (value < 0) goto hw_err;
 		value = log2(value & 0xff);
 		reg += value;
-		if(reg < 27) goto hw_err;
+		if (reg < 27) goto hw_err;
 		reg -= 27;
 		reg += (value << 2);
 
@@ -304,7 +304,7 @@
 	drt = pci_read_config32(ctrl->f0, DRT);
 	drt &= 3;  /* save bits 1:0 */
 
-	for(first_dimm = 0; first_dimm < 4; first_dimm++) {
+	for (first_dimm = 0; first_dimm < 4; first_dimm++) {
 		if (dimm_mask & (1 << first_dimm))
 			break;
 	}
@@ -313,7 +313,7 @@
 
 	drt |= (3<<18);  /* Trasmax */
 
-	for(cnt=0; cnt < 4; cnt++) {
+	for (cnt=0; cnt < 4; cnt++) {
 		if (!(dimm_mask & (1 << cnt))) {
 			continue;
 		}
@@ -322,7 +322,7 @@
 		latency = log2(reg) -2;
 
 		/* Loop through and find a fast clock with a low latency */
-		for(index = 0; index < 3; index++, latency++) {
+		for (index = 0; index < 3; index++, latency++) {
 			if ((latency < 2) || (latency > 4) ||
 				(!(reg & (1 << latency)))) {
 				continue;
@@ -330,8 +330,8 @@
 			value = spd_read_byte(ctrl->channel0[cnt],
 					latency_indicies[index]);
 
-			if(value <= cycle_time[drc&3]) {
-				if( latency > cas_latency) {
+			if (value <= cycle_time[drc&3]) {
+				if ( latency > cas_latency) {
 					cas_latency = latency;
 				}
 				break;
@@ -339,36 +339,36 @@
 		}
 	}
 	index = (cas_latency-2);
-	if((index)==0) cas_latency = 20;
-	else if((index)==1) cas_latency = 25;
+	if ((index)==0) cas_latency = 20;
+	else if ((index)==1) cas_latency = 25;
 	else cas_latency = 30;
 
-	for(cnt=0;cnt<4;cnt++) {
+	for (cnt=0;cnt<4;cnt++) {
 		if (!(dimm_mask & (1 << cnt))) {
 			continue;
 		}
 		reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
-		if(((index>>8)&0x0ff)<reg) {
+		if (((index>>8)&0x0ff)<reg) {
 			index &= ~(0x0ff << 8);
 			index |= (reg << 8);
 		}
 		reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
-		if(((index>>16)&0x0ff)<reg) {
+		if (((index>>16)&0x0ff)<reg) {
 			index &= ~(0x0ff << 16);
 			index |= (reg<<16);
 		}
 		reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
-		if(((index2>>0)&0x0ff)<reg) {
+		if (((index2>>0)&0x0ff)<reg) {
 			index2 &= ~(0x0ff << 0);
 			index2 |= (reg<<0);
 		}
 		reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
-		if(((index2>>8)&0x0ff)<reg) {
+		if (((index2>>8)&0x0ff)<reg) {
 			index2 &= ~(0x0ff << 8);
 			index2 |= (reg<<8);
 		}
 		reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
-		if(((index2>>16)&0x0ff)<reg) {
+		if (((index2>>16)&0x0ff)<reg) {
 			index2 &= ~(0x0ff << 16);
 			index2 |= (reg<<16);
 		}
@@ -376,22 +376,22 @@
 
 	/* get dimm speed */
 	value = cycle_time[drc&3];
-	if(value <= 0x50) {  /* 200 MHz */
-		if((index&7) > 2) {
+	if (value <= 0x50) {  /* 200 MHz */
+		if ((index&7) > 2) {
 			drt |= (2<<2);  /* CAS latency 4 */
 			cas_latency = 40;
 		} else {
 			drt |= (1<<2);  /* CAS latency 3 */
 			cas_latency = 30;
 		}
-		if((index&0x0ff00)<=0x03c00) {
+		if ((index&0x0ff00)<=0x03c00) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
 		} else {
 			drt |= (2<<8);  /* Trp RAS Precharg */
 		}
 
 		/* Trcd RAS to CAS delay */
-		if((index2&0x0ff)<=0x03c) {
+		if ((index2&0x0ff)<=0x03c) {
 			drt |= (0<<10);
 		} else {
 			drt |= (1<<10);
@@ -401,9 +401,9 @@
 		drt |= (1<<12);
 
 		/* Trc TRS min */
-		if((index2&0x0ff00)<=0x03700)
+		if ((index2&0x0ff00)<=0x03700)
 			drt |= (0<<14);
-		else if((index2&0xff00)<=0x03c00)
+		else if ((index2&0xff00)<=0x03c00)
 			drt |= (1<<14);
 		else
 			drt |= (2<<14); /* spd 41 */
@@ -411,20 +411,20 @@
 		drt |= (2<<16);  /* Twr not defined for DDR docs say use 2 */
 
 		/* Trrd Row Delay */
-		if((index&0x0ff0000)<=0x0140000) {
+		if ((index&0x0ff0000)<=0x0140000) {
 			drt |= (0<<20);
-		} else if((index&0x0ff0000)<=0x0280000) {
+		} else if ((index&0x0ff0000)<=0x0280000) {
 			drt |= (1<<20);
-		} else if((index&0x0ff0000)<=0x03c0000) {
+		} else if ((index&0x0ff0000)<=0x03c0000) {
 			drt |= (2<<20);
 		} else {
 			drt |= (3<<20);
 		}
 
 		/* Trfc Auto refresh cycle time */
-		if((index2&0x0ff0000)<=0x04b0000) {
+		if ((index2&0x0ff0000)<=0x04b0000) {
 			drt |= (0<<22);
-		} else if((index2&0x0ff0000)<=0x0690000) {
+		} else if ((index2&0x0ff0000)<=0x0690000) {
 			drt |= (1<<22);
 		} else {
 			drt |= (2<<22);
@@ -432,18 +432,18 @@
 		/* Docs say use 55 for all 200MHz */
 		drt |= (0x055<<24);
 	}
-	else if(value <= 0x60) { /* 167 MHz */
+	else if (value <= 0x60) { /* 167 MHz */
 		/* according to new documentation CAS latency is 00
 		 * for bits 3:2 for all 167 MHz
 		drt |= ((index&3)<<2); */  /* set CAS latency */
-		if((index&0x0ff00)<=0x03000) {
+		if ((index&0x0ff00)<=0x03000) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
 		} else {
 			drt |= (2<<8);  /* Trp RAS Precharg */
 		}
 
 		/* Trcd RAS to CAS delay */
-		if((index2&0x0ff)<=0x030) {
+		if ((index2&0x0ff)<=0x030) {
 			drt |= (0<<10);
 		} else {
 			drt |= (1<<10);
@@ -458,18 +458,18 @@
 		drt |= (2<<16);  /* Twr not defined for DDR docs say 2 */
 
 		/* Trrd Row Delay */
-		if((index&0x0ff0000)<=0x0180000) {
+		if ((index&0x0ff0000)<=0x0180000) {
 			drt |= (0<<20);
-		} else if((index&0x0ff0000)<=0x0300000) {
+		} else if ((index&0x0ff0000)<=0x0300000) {
 			drt |= (1<<20);
 		} else {
 			drt |= (2<<20);
 		}
 
 		/* Trfc Auto refresh cycle time */
-		if((index2&0x0ff0000)<=0x0480000) {
+		if ((index2&0x0ff0000)<=0x0480000) {
 			drt |= (0<<22);
-		} else if((index2&0x0ff0000)<=0x0780000) {
+		} else if ((index2&0x0ff0000)<=0x0780000) {
 			drt |= (2<<22);
 		} else {
 			drt |= (2<<22);
@@ -477,16 +477,16 @@
 		/* Docs state to use 99 for all 167 MHz */
 		drt |= (0x099<<24);
 	}
-	else if(value <= 0x75) { /* 133 MHz */
+	else if (value <= 0x75) { /* 133 MHz */
 		drt |= ((index&3)<<2);  /* set CAS latency */
-		if((index&0x0ff00)<=0x03c00) {
+		if ((index&0x0ff00)<=0x03c00) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
 		} else {
 			drt |= (2<<8);  /* Trp RAS Precharg */
 		}
 
 		/* Trcd RAS to CAS delay */
-		if((index2&0x0ff)<=0x03c) {
+		if ((index2&0x0ff)<=0x03c) {
 			drt |= (0<<10);
 		} else {
 			drt |= (1<<10);
@@ -501,25 +501,25 @@
 		drt |= (1<<16);  /* Twr not defined for DDR docs say 1 */
 
 		/* Trrd Row Delay */
-		if((index&0x0ff0000)<=0x01e0000) {
+		if ((index&0x0ff0000)<=0x01e0000) {
 			drt |= (0<<20);
-		} else if((index&0x0ff0000)<=0x03c0000) {
+		} else if ((index&0x0ff0000)<=0x03c0000) {
 			drt |= (1<<20);
 		} else {
 			drt |= (2<<20);
 		}
 
 		/* Trfc Auto refresh cycle time */
-		if((index2&0x0ff0000)<=0x04b0000) {
+		if ((index2&0x0ff0000)<=0x04b0000) {
 			drt |= (0<<22);
-		} else if((index2&0x0ff0000)<=0x0780000) {
+		} else if ((index2&0x0ff0000)<=0x0780000) {
 			drt |= (2<<22);
 		} else {
 			drt |= (2<<22);
 		}
 
 		/* Based on CAS latency */
-		if(index&7)
+		if (index&7)
 			drt |= (0x099<<24);
 		else
 			drt |= (0x055<<24);
@@ -549,7 +549,7 @@
 
 	/* 0x7c DRC */
 	drc = pci_read_config32(ctrl->f0, DRC);
-	for(cnt=0; cnt < 4; cnt++) {
+	for (cnt=0; cnt < 4; cnt++) {
 		if (!(dimm_mask & (1 << cnt))) {
 			continue;
 		}
@@ -616,7 +616,7 @@
 {
 	int i;
 	u8 b;
-	for(i=0;i<16;i++)
+	for (i=0;i<16;i++)
 		b=inb(0x80);
 }
 
@@ -637,18 +637,18 @@
 	/* ODT enable */
   	pci_write_config32(ctrl->f0, SDRC, 0x30000000);
 	/* Figure out which slots are Empty, Single, or Double sided */
-	for(i=0,t4=0,c2=0;i<8;i+=2) {
+	for (i=0,t4=0,c2=0;i<8;i+=2) {
 		c1 = pci_read_config8(ctrl->f0, DRB+i);
-		if(c1 == c2) continue;
+		if (c1 == c2) continue;
 		c2 = pci_read_config8(ctrl->f0, DRB+1+i);
-		if(c1 == c2)
+		if (c1 == c2)
 			t4 |= (1 << (i*4));
 		else
 			t4 |= (2 << (i*4));
 	}
-	for(i=0;i<1;i++) {
-	    if((t4&0x0f) == 1) {
-		if( ((t4>>8)&0x0f) == 0 ) {
+	for (i=0;i<1;i++) {
+	    if ((t4&0x0f) == 1) {
+		if ( ((t4>>8)&0x0f) == 0 ) {
 			data32 = 0x00000010; /* EEES */
 			break;
 		}
@@ -663,8 +663,8 @@
 		data32 = 0x77bbddee; /* SSSS */
 		break;
 	    }
-	    if((t4&0x0f) == 2) {
-		if( ((t4>>8)&0x0f) == 0 ) {
+	    if ((t4&0x0f) == 2) {
+		if ( ((t4>>8)&0x0f) == 0 ) {
 			data32 = 0x00003132; /* EEED */
 			break;
 		}
@@ -686,14 +686,14 @@
 
   	pci_write_config32(ctrl->f0, DDR2ODTC, data32);
 
-	for(dimm=0;dimm<8;dimm+=2) {
+	for (dimm=0;dimm<8;dimm+=2) {
 
 		write32(MCBAR+DCALADDR, 0x0b840001);
 		write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));
 
-		for(i=0;i<1001;i++) {
+		for (i=0;i<1001;i++) {
 			data32 = read32(MCBAR+DCALCSR);
-			if(!(data32 & (1<<31)))
+			if (!(data32 & (1<<31)))
 				break;
 		}
 	}
@@ -717,18 +717,18 @@
 	u32 work32h;
 	u32 data32r;
 	int32_t recen;
-	for(dimm=0;dimm<8;dimm+=1) {
+	for (dimm=0;dimm<8;dimm+=1) {
 
-		if(!(dimm&1)) {
+		if (!(dimm&1)) {
 			write32(MCBAR+DCALDATA+(17*4), 0x04020000);
 			write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));
 
-			for(i=0;i<1001;i++) {
+			for (i=0;i<1001;i++) {
 				data32 = read32(MCBAR+DCALCSR);
-				if(!(data32 & (1<<31)))
+				if (!(data32 & (1<<31)))
 					break;
 			}
-			if(i>=1000)
+			if (i>=1000)
 				continue;
 
 			dcal_data32_0 = read32(MCBAR+DCALDATA + 0);
@@ -744,56 +744,56 @@
 		}
 
 		/* check if bank is installed */
-		if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
+		if ((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
 			continue;
 		/* Calculate the timing value */
 		{
 		u32 bit;
-		for(i=0,edge=0,bit=63,cnt=31,data32r=0,
+		for (i=0,edge=0,bit=63,cnt=31,data32r=0,
 			work32l=dcal_data32_1,work32h=dcal_data32_3;
 				(i<4) && bit; i++) {
-			for(;;bit--,cnt--) {
-				if(work32l & (1<<cnt))
+			for (;;bit--,cnt--) {
+				if (work32l & (1<<cnt))
 					break;
-				if(!cnt) {
+				if (!cnt) {
 					work32l = dcal_data32_0;
 					work32h = dcal_data32_2;
 					cnt = 32;
 				}
-				if(!bit) break;
+				if (!bit) break;
 			}
-			for(;;bit--,cnt--) {
-				if(!(work32l & (1<<cnt)))
+			for (;;bit--,cnt--) {
+				if (!(work32l & (1<<cnt)))
 					break;
-				if(!cnt) {
+				if (!cnt) {
 					work32l = dcal_data32_0;
 					work32h = dcal_data32_2;
 					cnt = 32;
 				}
-				if(!bit) break;
+				if (!bit) break;
 			}
-			if(!bit) {
+			if (!bit) {
 				break;
 			}
 			data32 = ((bit%8) << 1);
-			if(work32h & (1<<cnt))
+			if (work32h & (1<<cnt))
 				data32 += 1;
-			if(data32 < 4) {
-				if(!edge) {
+			if (data32 < 4) {
+				if (!edge) {
 					edge = 1;
 				}
 				else {
-					if(edge != 1) {
+					if (edge != 1) {
 						data32 = 0x0f;
 					}
 				}
 			}
-			if(data32 > 12) {
-				if(!edge) {
+			if (data32 > 12) {
+				if (!edge) {
 					edge = 2;
 				}
 				else {
-					if(edge != 2) {
+					if (edge != 2) {
 						data32 = 0x00;
 					}
 				}
@@ -806,43 +806,43 @@
 		recen = data32r;
 		recen += 3;
 		recen = recen>>2;
-		for(cnt=5;cnt<24;) {
-			for(;;cnt++)
-				if(!(work32l & (1<<cnt)))
+		for (cnt=5;cnt<24;) {
+			for (;;cnt++)
+				if (!(work32l & (1<<cnt)))
 					break;
-			for(;;cnt++) {
-				if(work32l & (1<<cnt))
+			for (;;cnt++) {
+				if (work32l & (1<<cnt))
 					break;
 			}
 			data32 = (((cnt-1)%8)<<1);
-			if(work32h & (1<<(cnt-1))) {
+			if (work32h & (1<<(cnt-1))) {
 				data32++;
 			}
 			/* test for frame edge cross overs */
-			if((edge == 1) && (data32 > 12) &&
+			if ((edge == 1) && (data32 > 12) &&
 			    (((recen+16)-data32) < 3)) {
 				data32 = 0;
 				cnt += 2;
 			}
-			if((edge == 2) && (data32 < 4) &&
+			if ((edge == 2) && (data32 < 4) &&
 			    ((recen - data32) > 12))  {
 				data32 = 0x0f;
 				cnt -= 2;
 			}
-			if(((recen+3) >= data32) && ((recen-3) <= data32))
+			if (((recen+3) >= data32) && ((recen-3) <= data32))
 				break;
 		}
 		cnt--;
 		cnt /= 8;
 		cnt--;
-		if(recen&1)
+		if (recen&1)
 			recen+=2;
 		recen >>= 1;
 		recen += (cnt*8);
 		recen+=2;      /* this is not in the spec, but matches
 				 the factory output, and has less failure */
 		recen <<= (dimm/2) * 8;
-		if(!(dimm&1)) {
+		if (!(dimm&1)) {
 			recena |= recen;
 		}
 		else {
@@ -851,58 +851,58 @@
 	}
 	}
 	/* Check for Eratta problem */
-	for(i=cnt=0;i<32;i+=8) {
+	for (i=cnt=0;i<32;i+=8) {
 		if (((recena>>i)&0x0f)>7) {
 			cnt+= 0x101;
 		}
 		else {
-			if((recena>>i)&0x0f) {
+			if ((recena>>i)&0x0f) {
 				cnt++;
 			}
 		}
 	}
-	if(cnt&0x0f00) {
+	if (cnt&0x0f00) {
 		cnt = (cnt&0x0f) - (cnt>>16);
-		if(cnt>1) {
-			for(i=0;i<32;i+=8) {
-				if(((recena>>i)&0x0f)>7) {
+		if (cnt>1) {
+			for (i=0;i<32;i+=8) {
+				if (((recena>>i)&0x0f)>7) {
 					recena &= ~(0x0f<<i);
 					recena |= (7<<i);
 				}
 			}
 		}
 		else {
-			for(i=0;i<32;i+=8) {
-				if(((recena>>i)&0x0f)<8) {
+			for (i=0;i<32;i+=8) {
+				if (((recena>>i)&0x0f)<8) {
 					recena &= ~(0x0f<<i);
 					recena |= (8<<i);
 				}
 			}
 		}
 	}
-	for(i=cnt=0;i<32;i+=8) {
+	for (i=cnt=0;i<32;i+=8) {
 		if (((recenb>>i)&0x0f)>7) {
 			cnt+= 0x101;
 		}
 		else {
-			if((recenb>>i)&0x0f) {
+			if ((recenb>>i)&0x0f) {
 				cnt++;
 			}
 		}
 	}
-	if(cnt & 0x0f00) {
+	if (cnt & 0x0f00) {
 		cnt = (cnt&0x0f) - (cnt>>16);
-		if(cnt>1) {
-			for(i=0;i<32;i+=8) {
-				if(((recenb>>i)&0x0f)>7) {
+		if (cnt>1) {
+			for (i=0;i<32;i+=8) {
+				if (((recenb>>i)&0x0f)>7) {
 					recenb &= ~(0x0f<<i);
 					recenb |= (7<<i);
 				}
 			}
 		}
 		else {
-			for(i=0;i<32;i+=8) {
-				if(((recenb>>8)&0x0f)<8) {
+			for (i=0;i<32;i+=8) {
+				if (((recenb>>8)&0x0f)<8) {
 					recenb &= ~(0x0f<<i);
 					recenb |= (8<<i);
 				}
@@ -978,7 +978,7 @@
 		0x00410000 | CONFIG_DIMM_MAP_LOGICAL);
 	/* set dram type and Front Side Bus freq. */
 	drc = spd_set_dram_controller_mode(ctrl, mask);
-	if( drc == 0) {
+	if ( drc == 0) {
 		die("Error calculating DRC\n");
 	}
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
@@ -986,7 +986,7 @@
 	data32 = data32 | (1 << 5);  /* temp turn off ODT */
   	/* Set gearing, then dram controller mode */
   	/* drc bits 3:2 = FSB speed */
-  	for(iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) {
+  	for (iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) {
   		pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
 	}
 	/* 0x7c DRC */
@@ -1011,7 +1011,7 @@
 		/* program DRT timing values */
 	cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
 
-	for(i=0;i<8;i+=2) { /* loop through each dimm to test */
+	for (i=0;i<8;i+=2) { /* loop through each dimm to test */
 		printk(BIOS_DEBUG, "DIMM %08x\n", i);
 		/* Apply NOP */
 		do_delay();
@@ -1020,115 +1020,115 @@
 		write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
 
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 
 	/* Apply NOP */
 	do_delay();
 
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, 0x04000000);
 		write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 
 	/* EMRS dll's enabled */
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		/* fixme hard code AL additive latency */
 		write32(MCBAR+DCALADDR, 0x0b940001);
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 	/* MRS reset dll's */
 	do_delay();
-	if(cas_latency == 30)
+	if (cas_latency == 30)
 		mode_reg = 0x053a0000;
 	else
 		mode_reg = 0x054a0000;
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, mode_reg);
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 
 	/* Precharg all banks */
 	do_delay();
 	do_delay();
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, 0x04000000);
 		write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 
 	/* Do 2 refreshes */
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 	do_delay();
 	/* for good luck do 6 more */
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
 	}
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
 	}
 	do_delay();
 	/* MRS reset dll's normal */
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 
 	/* Do only if DDR2  EMRS dll's enabled */
 	do_delay();
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALADDR, (0x0b940001));
 		write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 
 	do_delay();
@@ -1143,7 +1143,7 @@
 
 	/* DQS */
 	pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
-	for(i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) {
+	for (i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) {
 		write32(cntptr, dqs_data[i]);
 	}
 	pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
@@ -1156,14 +1156,14 @@
 
 	/* clear memory and init ECC */
 	printk(BIOS_DEBUG, "Clearing memory\n");
-	for(i=0;i<64;i+=4) {
+	for (i=0;i<64;i+=4) {
 		write32(MCBAR+DCALDATA+i, 0x00000000);
 	}
 
-	for(cs=0;cs<8;cs+=2) {
+	for (cs=0;cs<8;cs+=2) {
 		write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
 		do data32 = read32(MCBAR+DCALCSR);
-		while(data32 & 0x80000000);
+		while (data32 & 0x80000000);
 	}
 
 	/* Bring memory subsystem on line */
@@ -1172,9 +1172,9 @@
 	pci_write_config32(ctrl->f0, 0x98, data32);
 	/* wait for completion */
 	printk(BIOS_DEBUG, "Waiting for mem complete\n");
-	while(1) {
+	while (1) {
 		data32 = pci_read_config32(ctrl->f0, 0x98);
-		if( (data32 & (1<<31)) == 0)
+		if ( (data32 & (1<<31)) == 0)
 			break;
 	}
 	printk(BIOS_DEBUG, "Done\n");
diff --git a/src/northbridge/intel/i3100/reset_test.c b/src/northbridge/intel/i3100/reset_test.c
index de86f80..1ea62c0 100644
--- a/src/northbridge/intel/i3100/reset_test.c
+++ b/src/northbridge/intel/i3100/reset_test.c
@@ -12,7 +12,7 @@
 
 	dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
 
-	if( (dword & DRC_DONE) != 0 ) {
+	if ( (dword & DRC_DONE) != 0 ) {
 		return 1;
 	}
 
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index efd4326..064df5b 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -10,13 +10,13 @@
 {
 	int i;
 	printk(BIOS_DEBUG, "\n");
-	for(i = 0; i < DIMM_SOCKETS; i++) {
+	for (i = 0; i < DIMM_SOCKETS; i++) {
 		unsigned device;
 		device = DIMM0 + i;
 		if (device) {
 			int j;
 			printk(BIOS_DEBUG, "DIMM %d: %02x", i, device);
-			for(j = 0; j < 256; j++) {
+			for (j = 0; j < 256; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 0032668..66282aa 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -697,12 +697,12 @@
 	/* It is possible to partially use larger then supported
 	 * modules by setting them to a supported size.
 	 */
-	if(sz.side1 > 128) {
+	if (sz.side1 > 128) {
 		PRINT_DEBUG("Side1 was %dMB but only 128MB will be used.\n",
 			sz.side1);
 		sz.side1 = 128;
 
-		if(sz.side2 > 128) {
+		if (sz.side2 > 128) {
 			PRINT_DEBUG("Side2 was %dMB but only 128MB will be used.\n",
 				sz.side2);
 			sz.side2 = 128;
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index 1021fce..ef49380 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -36,7 +36,7 @@
 	struct i5000_fbd_channel *c;
 	int ret;
 
-	for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
+	for (c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
 		if (c->used && (ret = cb(c)))
 			return ret;
 	return 0;
@@ -48,7 +48,7 @@
 	struct i5000_fbd_branch *b;
 	int ret;
 
-	for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
+	for (b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
 		if (b->used && (ret = cb(b)))
 			return ret;
 	return 0;
@@ -60,7 +60,7 @@
 	struct i5000_fbdimm *d;
 	int ret, i;
 
-	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+	for (i = 0; i < I5000_MAX_DIMMS; i++) {
 		d = setup->dimms[i];
 		if ((ret = cb(d))) {
 			return ret;
@@ -75,7 +75,7 @@
 	struct i5000_fbdimm *d;
 	int ret, i;
 
-	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+	for (i = 0; i < I5000_MAX_DIMMS; i++) {
 		d = setup->dimms[i];
 		if (d->present && (ret = cb(d)))
 			return ret;
@@ -91,12 +91,12 @@
 	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
 	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
 
-	while(count-- > 0) {
+	while (count-- > 0) {
 		pci_write_config32(dev, cmdreg, 0xa8000000 |	\
 				   (d->num & 0x03) << 24 | addr++ << 16);
 
 		int timeout = 1000;
-		while((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY && timeout--)
+		while ((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY && timeout--)
 			udelay(10);
 
 		if (status & I5000_SPD_SBE || !timeout)
@@ -345,7 +345,7 @@
 	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
 			   (byte1 << 16) | (byte2 << 8) | 1);
 
-	while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)
+	while (((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)
 		udelay(10);
 
 	if (status & I5000_SPD_WOD && timeout)
@@ -353,7 +353,7 @@
 
 	printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
 	       d->branch->num, d->channel->num, d->num, byte1, byte2, status);
-	for(;;);
+	for (;;);
 	return -1;
 }
 
@@ -368,7 +368,7 @@
 	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
 			   (byte1 << 16));
 
-	while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)
+	while (((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--)
 		udelay(10);
 
 	if ((status & I5000_SPD_RDO) && timeout)
@@ -494,7 +494,7 @@
 	i5000_amb_write_config32(d, 4, AMB_DCALCSR, command);
 
 	udelay(1000);
-	while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
+	while ((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
 	      & (1 << 31));
 
 	if (status & (1 << 30)) {
@@ -512,10 +512,10 @@
 
 	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
 	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
-	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+	while ((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
 
 	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
-	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+	while ((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
 
 	if (ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
 	    ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
@@ -530,7 +530,7 @@
 	u32 val;
 	u8 odt;
 
-	for(rank = 0; rank < d->ranks; rank++) {
+	for (rank = 0; rank < d->ranks; rank++) {
 		printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
 		       d->branch->num, d->channel->num, d->num, rank);
 
@@ -666,7 +666,7 @@
 
 	printk(BIOS_DEBUG, "waiting for new state...");
 
-	while(pci_read_config8(dev, I5000_FBDST) != state && timeout--)
+	while (pci_read_config8(dev, I5000_FBDST) != state && timeout--)
 		udelay(10);
 
 	if (timeout) {
@@ -685,7 +685,7 @@
 				c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
 
 	printk(BIOS_DEBUG, "      waiting for pattern recognition...");
-	while(pci_read_config16(dev, 0) != 0x1fff && --i > 0)
+	while (pci_read_config16(dev, 0) != 0x1fff && --i > 0)
 		udelay(5000);
 
 	printk(BIOS_DEBUG, i ?  "done\n" : "failed\n");
@@ -723,7 +723,7 @@
 	device_t branchdev = c->branch->branchdev;
 	u16 ambpresent = 0x8000;
 
-	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+	for (i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
 		if (c->dimm[i].present)
 			ambpresent |= (1 << i);
 	}
@@ -772,7 +772,7 @@
 	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
 		return -1;
 
-	for(i = 0; i < highest_amb; i++) {
+	for (i = 0; i < highest_amb; i++) {
 		if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
 			return -1;
 	}
@@ -807,7 +807,7 @@
 	pci_write_config8(c->branch->branchdev,
 			       c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
 
-	for(i = 0; i < 4; i++) {
+	for (i = 0; i < 4; i++) {
 		if (c->dimm[i].present)
 			i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? (fbdsbcfg | 0x1000) : fbdsbcfg);
 	}
@@ -1040,7 +1040,7 @@
 	int cnt = 1000;
 	u32 res;
 
-	while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
+	while ((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
 		udelay(1000);
 
 	if (cnt && !(res & (1 << 30)))
@@ -1153,7 +1153,7 @@
 {
 	int i, dmir = 0, set = 0;
 
-	for(i = 7; set < limit && i >= 0; i--) {
+	for (i = 7; set < limit && i >= 0; i--) {
 		if (!(*rankmap & (1 << i)))
 			continue;
 
@@ -1194,7 +1194,7 @@
 	if (!b->used)
 		return 0;
 
-	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+	for (i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
 		rankmap >>= 2;
 		d = b->channel[0].dimm + i;
 
@@ -1219,7 +1219,7 @@
 	if (!b->setup->single_channel)
 		ranksize <<= 1;
 
-	while(ranks) {
+	while (ranks) {
 
 		if (ranks >= 4)
 			dmirval = get_dmir(&rankmap, &set, 4);
@@ -1240,7 +1240,7 @@
 		dmir += 4;
 	}
 
-	for(; dmir <= I5000_DMIR4; dmir += 4) {
+	for (; dmir <= I5000_DMIR4; dmir += 4) {
 		printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
 		       dmirval);
 		pci_write_config32(dev, dmir, dmirval);
@@ -1366,19 +1366,19 @@
 	   support it, it will decrease this setting in spd_read */
 	setup->ddr_speed = DDR_667MHZ;
 
-	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+	for (branch = 0; branch < I5000_MAX_BRANCH; branch++) {
 		b = setup->branch + branch;
 		b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
 		b->setup = setup;
 		b->num = branch;
 
-		for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
+		for (channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
 			c = b->channel + channel;
 			c->branch = b;
 			c->setup = setup;
 			c->num = channel;
 
-			for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
+			for (dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
 				d = c->dimm + dimm;
 				setup->dimms[i++] = d;
 				d->channel = c;
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index b74bb36..1b45bc2 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -10,13 +10,13 @@
 {
 	int i;
 	printk(BIOS_DEBUG, "\n");
-	for(i = 0; i < DIMM_SOCKETS; i++) {
+	for (i = 0; i < DIMM_SOCKETS; i++) {
 		unsigned device;
 		device = DIMM0 + i;
 		if (device) {
 			int j;
 			printk(BIOS_DEBUG, "DIMM %d: %02x", i, device);
-			for(j = 0; j < 256; j++) {
+			for (j = 0; j < 256; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index a832dda..05e934d 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -25,7 +25,7 @@
 static inline void print_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
+	for (dev = PCI_DEV(0, 0, 0);
 		dev <= PCI_DEV(0, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
@@ -46,7 +46,7 @@
 	print_debug_pci_dev(dev);
 	printk(BIOS_DEBUG, "\n");
 
-	for(i = 0; i <= 255; i++) {
+	for (i = 0; i <= 255; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0)
 			printk(BIOS_DEBUG, "%02x:", i);
@@ -60,7 +60,7 @@
 static inline void dump_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
+	for (dev = PCI_DEV(0, 0, 0);
 		dev <= PCI_DEV(0, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
@@ -78,13 +78,13 @@
 {
 	int i;
 	printk(BIOS_DEBUG, "\n");
-	for(i = 0; i < 2; i++) {
+	for (i = 0; i < 2; i++) {
 		unsigned device;
 		device = DIMM0 + i;
 		if (device) {
 			int j;
 			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-			for(j = 0; j < 256; j++) {
+			for (j = 0; j < 256; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0)
@@ -106,12 +106,12 @@
 {
         int i;
         printk(BIOS_DEBUG, "\n");
-        for(i = 1; i < 0x80; i++) {
+        for (i = 1; i < 0x80; i++) {
                 unsigned device;
                 device = i;
                 int j;
                 printk(BIOS_DEBUG, "smbus: %02x", device);
-                for(j = 0; j < 256; j++) {
+                for (j = 0; j < 256; j++) {
                 	int status;
                         unsigned char byte;
                         if ((j & 0xf) == 0)
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 4789663..fe6059d 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -447,7 +447,7 @@
 
 	/* 8 CBR refreshes (Auto Refresh) */
 	PRINTK_DEBUG(" 8 CBR refreshes\n");
-	for(i = 0; i < 8; i++) {
+	for (i = 0; i < 8; i++) {
 		do_ram_command(RAM_COMMAND_CBR, 0);
 		delay();
 		delay();
diff --git a/src/northbridge/intel/i855/reset_test.c b/src/northbridge/intel/i855/reset_test.c
index 7902911..9ca7854 100644
--- a/src/northbridge/intel/i855/reset_test.c
+++ b/src/northbridge/intel/i855/reset_test.c
@@ -27,7 +27,7 @@
 
 	dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
 
-	if( (dword & DRC_DONE) != 0 ) {
+	if ( (dword & DRC_DONE) != 0 ) {
 		return 1;
 	}
 
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index d26e84e..5b6c87a 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -24,7 +24,7 @@
 void print_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
+	for (dev = PCI_DEV(0, 0, 0);
 		dev <= PCI_DEV(0, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
@@ -46,7 +46,7 @@
 
 	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
 
-	for(i = 0; i <= 255; i++) {
+	for (i = 0; i <= 255; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
 			printk(BIOS_DEBUG, "%02x:", i);
@@ -62,7 +62,7 @@
 void dump_pci_devices(void)
 {
 	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0);
+	for (dev = PCI_DEV(0, 0, 0);
 		dev <= PCI_DEV(0, 0x1f, 0x7);
 		dev += PCI_DEV(0,0,1)) {
 		uint32_t id;
@@ -80,12 +80,12 @@
 {
         unsigned device;
         device = DIMM0;
-        while(device <= DIMM3) {
+        while (device <= DIMM3) {
                 int status = 0;
                 int i;
         	printk(BIOS_DEBUG, "\ndimm %02x", device);
 
-                for(i = 0; (i < 256) ; i++) {
+                for (i = 0; (i < 256) ; i++) {
                         if ((i % 16) == 0) {
 				printk(BIOS_DEBUG, "\n%02x: ", i);
                         }
@@ -105,8 +105,8 @@
 {
         unsigned i;
 	printk(BIOS_DEBUG, "dump_mem:");
-        for(i=start;i<end;i++) {
-		if((i & 0xf)==0) {
+        for (i=start;i<end;i++) {
+		if ((i & 0xf)==0) {
 			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
 		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 27acef3..8c674e9 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -469,7 +469,7 @@
 						  SPD_ACCEPTABLE_CAS_LATENCIES);
 	}
 
-	if(!cas_mask) {
+	if (!cas_mask) {
 		die("No DDR-II modules with accepted CAS latencies found.\n");
 	}
 
@@ -632,7 +632,7 @@
 			tRAS_cycles++;
 		}
 	}
-	if(tRAS_cycles > 0x18) {
+	if (tRAS_cycles > 0x18) {
 		die("DDR-II Module does not support this frequency (tRAS error)\n");
 	}
 
@@ -673,7 +673,7 @@
 		}
 	}
 
-	if(tRP_cycles > 6) {
+	if (tRP_cycles > 6) {
 		die("DDR-II Module does not support this frequency (tRP error)\n");
 	}
 
@@ -713,7 +713,7 @@
 			tRCD_cycles++;
 		}
 	}
-	if(tRCD_cycles > 6) {
+	if (tRCD_cycles > 6) {
 		die("DDR-II Module does not support this frequency (tRCD error)\n");
 	}
 
@@ -753,7 +753,7 @@
 			tWR_cycles++;
 		}
 	}
-	if(tWR_cycles > 5) {
+	if (tWR_cycles > 5) {
 		die("DDR-II Module does not support this frequency (tWR error)\n");
 	}
 
@@ -1466,7 +1466,7 @@
 {
 	int i;
 
-	for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
+	for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
 		struct dimm_size sz;
 
 		sysinfo->banksize[i * 2] = 0;
@@ -1508,7 +1508,7 @@
 	printk(BIOS_DEBUG, "Setting RAM size...\n");
 
 	cum0 = 0;
-	for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
+	for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
 		cum0 += sysinfo->banksize[i];
 		MCHBAR8(C0DRB0+i) = cum0;
 	}
@@ -1527,7 +1527,7 @@
 		cum1 = 0;
 #endif
 
-	for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
+	for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
 		cum1 += sysinfo->banksize[i + 4];
 		MCHBAR8(C1DRB0+i) = cum1;
 	}
@@ -1562,7 +1562,7 @@
 	u16 dra0=0, dra1=0, dra = 0;
 
 	printk(BIOS_DEBUG, "Setting row attributes...\n");
-	for(i=0; i < 2 * DIMM_SOCKETS; i++) {
+	for (i=0; i < 2 * DIMM_SOCKETS; i++) {
 		u16 device;
 		u8 columnsrows;
 
@@ -1908,7 +1908,7 @@
 	reg32 = MCHBAR32(DCC);
 	reg32 &= ~(7 << 0);
 
-	if(sysinfo->interleaved) {
+	if (sysinfo->interleaved) {
 		/* Dual Channel Interleaved */
 		printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
 		reg32 |= (1 << 1);
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index afe6199..f4d9315 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -273,7 +273,7 @@
 /**
  * Here we use a trick. The RCVEN channel 0 registers are all at an
  * offset of 0x80 to the channel 0 registers. We don't want to waste
- * a lot of if()s so let's just pass 0 or 0x80 for the channel offset.
+ * a lot of if ()s so let's just pass 0 or 0x80 for the channel offset.
  */
 
 static int receive_enable_autoconfig(int channel_offset,
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index e4957d2..e1d23a5 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -521,7 +521,7 @@
 	}
 	if (highcas < lowcas) {
 		// Timings not supported by MCH, lower the frequency
-		if(freq == MEM_CLOCK_800MHz) {
+		if (freq == MEM_CLOCK_800MHz) {
 			freq--;
 			PRINTK_DEBUG("Run DDR clock speed reduced due to timings\n");
 		} else {
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 421763c..45bf476 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -278,7 +278,7 @@
 
 	memset(mem_info, 0, sizeof(*mem_info));
 
-	FOR_ALL_CHANNELS for(slot = 0; slot < NUM_SLOTS; slot++) {
+	FOR_ALL_CHANNELS for (slot = 0; slot < NUM_SLOTS; slot++) {
 		dimm = &mem_info->dimm[mem_info->dimm_cnt];
 		if (info->dimm[channel][slot].size_mb) {
 			dimm->ddr_type = MEMORY_TYPE_DDR3;
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index ed6ab60..352e71c 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -774,13 +774,13 @@
 		if (!CHANNEL_IS_POPULATED(s->dimms, i)) {
 			printk(BIOS_DEBUG, "No dimms in channel %d\n", i);
 			reg8 = 0x3f;
-		} else if(ONLY_DIMMA_IS_POPULATED(s->dimms, i)) {
+		} else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) {
 			printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i);
 			reg8 = 0x38;
-		} else if(ONLY_DIMMB_IS_POPULATED(s->dimms, i)) {
+		} else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) {
 			printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i);
 			reg8 =  0x7;
-		} else if(BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
+		} else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
 			printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i);
 			reg8 = 0;
 		} else {
@@ -960,7 +960,7 @@
 		i = (i + 10) % 14;
 		MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;
 		MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;
-		while(MCHBAR8(0x180) & 0x10);
+		while (MCHBAR8(0x180) & 0x10);
 	}
 
 	reg8 = MCHBAR8(0x188) & ~1;