tree 09f139eef3c18ea0f2f7128f4b592e393a7f6ac7
parent 8fc6d18fc0ae1c47718ee51c86d38193b12e6e5d
author Michał Żygowski <michal.zygowski@3mdeb.com> 1692609124 +0200
committer Felix Singer <service+coreboot-gerrit@felixsinger.de> 1692652613 +0000

soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSP

PchPcieClockGating and PchPciePowerGating UPDs are not yet available
in RPL-S IOT FSP. It also looks like those UPDs are not generally
available in all public RaptorLake FSP headers yet, so guard it
against SOC_INTEL_RAPTORLAKE to avoid build errors.

Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>