soc/intel/xeon_sp: Use native CAR teardown
This cleans up the postcar frame setup, which now gets used instead of
just going with TempRamExit MTRR's.
Note that ramstage CPU init sets up different final MTRRs anyway.
TESTED on ocp/deltalake and ocp/tiogapass.
Change-Id: I756c2d479fef859a460696300422f08013a300f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 6c10c35..d84a80e 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -67,6 +67,8 @@
select HAVE_SMI_HANDLER
select X86_SMM_LOADER_VERSION2
select REG_SCRIPT
+ select NO_FSP_TEMP_RAM_EXIT
+ select INTEL_CAR_NEM # For postcar only now
config MAINBOARD_USES_FSP2_0
bool