diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 8804ce8..9adbca1 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -124,7 +124,7 @@
 	/* (DRAM Read Timing Control, if similar to 855PM?)
 	 * 0x80 - 0x81   documented differently for e7505
 	 * This register has something to do with CAS latencies,
-	 * possibily this is the real chipset control.
+	 * possibly this is the real chipset control.
 	 * At 0x00 CAS latency 1.5 works.
 	 * At 0x06 CAS latency 2.5 works.
 	 * At 0x01 CAS latency 2.0 works.
@@ -755,7 +755,7 @@
 }
 
 /*-----------------------------------------------------------------------------
-DIMM-independant configuration functions:
+DIMM-independent configuration functions:
 -----------------------------------------------------------------------------*/
 
 /**
@@ -1406,7 +1406,7 @@
 				  SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
 		die_on_spd_error(value);
 		if (value >= 0xa0) {	/* At 133MHz this constant should be 0x75 */
-			controller_mode &= ~(1 << 16);	/* Use two clock cyles instead of one */
+			controller_mode &= ~(1 << 16);	/* Use two clock cycles instead of one */
 		}
 #endif
 
@@ -1498,7 +1498,7 @@
 	pci_write_config8(MCHDEV, CKDIS, clock_disable);
 }
 
-/* DIMM-dedependent configuration functions */
+/* DIMM-dependent configuration functions */
 
 /**
  * DDR Receive FIFO RE-Sync (?)
diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c
index cda9e08..affbbc6 100644
--- a/src/northbridge/intel/fsp_sandybridge/gma.c
+++ b/src/northbridge/intel/fsp_sandybridge/gma.c
@@ -26,7 +26,7 @@
 
 /* some vga option roms are used for several chipsets but they only have one
  * PCI ID in their header. If we encounter such an option rom, we need to do
- * the mapping ourselfes
+ * the mapping ourselves
  */
 
 u32 map_oprom_vendev(u32 vendev)
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index fb40b94..10c64e9 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -15,7 +15,7 @@
 	 * MCFG. This code also assumes that bootblock_northbridge_init() is
 	 * the first thing called in the non-asm boot block code. The final
 	 * assumption is that no assembly code is using the
-	 * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+	 * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses.
 	 *
 	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
 	 * 4GiB.
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 5a30f87..ae1863b 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -119,7 +119,7 @@
 	unsigned int	page_size; /* of whole DIMM in Bytes (4096 or 8192) */
 	unsigned int	banks;
 	unsigned int	ranks;
-	unsigned int	rank_capacity_mb; /* per rank in Mega Bytes */
+	unsigned int	rank_capacity_mb; /* per rank in Megabytes */
 } dimminfo_t;
 
 /* The setup is one DIMM per channel, so there's no need to find a
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 167ef24..daddbab 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -198,7 +198,7 @@
 /*
  * Detect if the system went through an interrupted RAM init or is incon-
  * sistent. If so, initiate a cold reboot. Otherwise mark the system to be
- * in RAM init, so this function would detect it on an erreneous reboot.
+ * in RAM init, so this function would detect it on an erroneous reboot.
  */
 void enter_raminit_or_reset(void)
 {
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 1c7aff9..04fa6da 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -93,7 +93,7 @@
 
 /* some vga option roms are used for several chipsets but they only have one
  * PCI ID in their header. If we encounter such an option rom, we need to do
- * the mapping ourselfes
+ * the mapping ourselves
  */
 
 u32 map_oprom_vendev(u32 vendev)
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
index d51692c..d3e88f2 100644
--- a/src/northbridge/intel/haswell/ram_calc.c
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -24,7 +24,7 @@
 {
 	/*
 	 * Base of TSEG is top of usable DRAM below 4GiB. The register has
-	 * 1 MiB alignement.
+	 * 1 MiB alignment.
 	 */
 	uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
 	return tom & ~((1 << 20) - 1);
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index a48d8fe..8025ac3 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -93,7 +93,7 @@
 			/* Find the offset of the remap window from tolm */
 			remapoffsetk = remapbasek - tolmk;
 		}
-		/* Write the RAM configruation registers,
+		/* Write the RAM configuration registers,
 		 * preserving the reserved bits.
 		 */
 		tolm_r = pci_read_config16(mc_dev, 0xc4);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 33471ef..aebe4e8 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -92,7 +92,7 @@
 
 	/* Note it might be easier to use byte 31 here, it has the DIMM size as
 	 * a multiple of 4MB.  The way we do it now we can size both
-	 * sides of an assymetric dimm.
+	 * sides of an asymmetric dimm.
 	 */
 	value = spd_read_byte(device, 3);	/* rows */
 	if (value < 0) goto hw_err;
@@ -385,9 +385,9 @@
 			cas_latency = 30;
 		}
 		if ((index & 0x0ff00) <= 0x03c00) {
-			drt |= (1<<8); /* Trp RAS Precharg */
+			drt |= (1<<8); /* Trp RAS Precharge */
 		} else {
-			drt |= (2<<8); /* Trp RAS Precharg */
+			drt |= (2<<8); /* Trp RAS Precharge */
 		}
 
 		/* Trcd RAS to CAS delay */
@@ -437,9 +437,9 @@
 		 * for bits 3:2 for all 167 MHz
 		drt |= ((index & 3)<<2); */ /* set CAS latency */
 		if ((index & 0x0ff00) <= 0x03000) {
-			drt |= (1<<8); /* Trp RAS Precharg */
+			drt |= (1<<8); /* Trp RAS Precharge */
 		} else {
-			drt |= (2<<8); /* Trp RAS Precharg */
+			drt |= (2<<8); /* Trp RAS Precharge */
 		}
 
 		/* Trcd RAS to CAS delay */
@@ -480,9 +480,9 @@
 	else if (value <= 0x75) { /* 133 MHz */
 		drt |= ((index & 3)<<2); /* set CAS latency */
 		if ((index & 0x0ff00) <= 0x03c00) {
-			drt |= (1<<8); /* Trp RAS Precharg */
+			drt |= (1<<8); /* Trp RAS Precharge */
 		} else {
-			drt |= (2<<8); /* Trp RAS Precharg */
+			drt |= (2<<8); /* Trp RAS Precharge */
 		}
 
 		/* Trcd RAS to CAS delay */
@@ -850,7 +850,7 @@
 		}
 	}
 	}
-	/* Check for Eratta problem */
+	/* Check for Errata problem */
 	for (i = cnt = 0; i < 32; i+=8) {
 		if (((recena>>i)&0x0f)>7) {
 			cnt+= 0x101;
@@ -1032,7 +1032,7 @@
 		while (data32 & 0x80000000);
 	}
 
-	/* Precharg all banks */
+	/* Precharge all banks */
 	do_delay();
 	for (cs = 0; cs < 8; cs+=2) {
 		write32(MCBAR+DCALADDR, 0x04000000);
@@ -1063,7 +1063,7 @@
 		while (data32 & 0x80000000);
 	}
 
-	/* Precharg all banks */
+	/* Precharge all banks */
 	do_delay();
 	do_delay();
 	do_delay();
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index f9fd816..e217c23 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -173,10 +173,10 @@
 	 * 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS
 	 * 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS
 	 * 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS
-	 * 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS entension
-	 * 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS entension
-	 * 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS entension
-	 * 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS entension
+	 * 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS extension
+	 * 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS extension
+	 * 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS extension
+	 * 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS extension
 	 *
 	 * Bit assignment:
 	 * 00 = DRAM Disabled (all access goes to memory mapped I/O space)
@@ -587,7 +587,7 @@
 }
 
 /*-----------------------------------------------------------------------------
-DIMM-independant configuration functions.
+DIMM-independent configuration functions.
 -----------------------------------------------------------------------------*/
 
 static void spd_enable_refresh(void)
@@ -680,7 +680,7 @@
 
 	/*
 	 * SPD byte 31 is the memory size divided by 4 so we
-	 * need to muliply by 4 to get the total size.
+	 * need to multiply by 4 to get the total size.
 	 */
 	sz.side1 *= 4;
 	sz.side2 *= 4;
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index 1a802b0..b8925b2 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -1318,7 +1318,7 @@
 		((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) |
 		(1 << 8) | /* enhanced scrub mode */
 		(1 << 7) | /* enable patrol scrub */
-		(1 << 6) | /* enable demand scrubing */
+		(1 << 6) | /* enable demand scrubbing */
 		(1 << 5); /* enable northbound error detection */
 
 	printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
@@ -1393,7 +1393,7 @@
 
 static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
 {
-	/* register write captured from vendor BIOS, but undocument by Intel */
+	/* register write captured from vendor BIOS, but undocumented by Intel */
 	pci_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
 
 	pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 24ffd94..83ef883 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -204,7 +204,7 @@
 }
 
 /*-----------------------------------------------------------------------------
-DIMM-independant configuration functions.
+DIMM-independent configuration functions.
 -----------------------------------------------------------------------------*/
 
 /*
@@ -244,14 +244,14 @@
 
 			/* This array is provided in raminit.h, because it got
 			 * extremely messy. The above way is cleaner, but
-			 * doesn't support any asymetrical/odd configurations.
+			 * doesn't support any asymmetrical/odd configurations.
 			 */
 			dimm_size = translate_spd_to_i82810[dimm_size];
 
 			printk(BIOS_DEBUG, "After translation, dimm_size is %d\n", dimm_size);
 
 			/* If the DIMM is dual-sided, the DRP value is +2 */
-			/* TODO: Figure out asymetrical configurations. */
+			/* TODO: Figure out asymmetrical configurations. */
 			if ((smbus_read_byte(DIMM0 + i, 127) | 0xf) ==
 			    0xff) {
 				printk(BIOS_DEBUG, "DIMM is dual-sided\n");
diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h
index 74520b1..a4b0a86 100644
--- a/src/northbridge/intel/i82830/i82830.h
+++ b/src/northbridge/intel/i82830/i82830.h
@@ -21,13 +21,13 @@
 #define GCC0    0x50 /* GMCH Control #0 (0xa072) */
 #define GCC1    0x52 /* GMCH Control #1 (0x0000) */
 #define FDHC    0x58 /* Fixed DRAM Hole Control (0x00) */
-#define PAM0    0x59 /* Programable Attribute Map #0 (0x00) */
-#define PAM1    0x5a /* Programable Attribute Map #1 (0x00) */
-#define PAM2    0x5b /* Programable Attribute Map #2 (0x00) */
-#define PAM3    0x5c /* Programable Attribute Map #3 (0x00) */
-#define PAM4    0x5d /* Programable Attribute Map #4 (0x00) */
-#define PAM5    0x5e /* Programable Attribute Map #5 (0x00) */
-#define PAM6    0x5f /* Programable Attribute Map #6 (0x00) */
+#define PAM0    0x59 /* Programmable Attribute Map #0 (0x00) */
+#define PAM1    0x5a /* Programmable Attribute Map #1 (0x00) */
+#define PAM2    0x5b /* Programmable Attribute Map #2 (0x00) */
+#define PAM3    0x5c /* Programmable Attribute Map #3 (0x00) */
+#define PAM4    0x5d /* Programmable Attribute Map #4 (0x00) */
+#define PAM5    0x5e /* Programmable Attribute Map #5 (0x00) */
+#define PAM6    0x5f /* Programmable Attribute Map #6 (0x00) */
 #define DRB     0x60 /* DRAM Row Boundary #0 (0x00) */
 #define DRB1    0x61 /* DRAM Row Boundary #1 (0x00) */
 #define DRB2    0x62 /* DRAM Row Boundary #2 (0x00) */
@@ -46,7 +46,7 @@
 #define ERRCMD  0x94 /* Error Command (0x0000) */
 #define BUFF_SC 0xec /* System Memory Buffer Strength Control (0x00000000) */
 #define APBASE  0x10 /* Aperture Base Configuration (0x00000008) */
-#define APSIZE  0xb4 /* Apterture Size (0x00) */
+#define APSIZE  0xb4 /* Aperture Size (0x00) */
 #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */
 
 #endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index bd92ac1..7850c87 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -159,7 +159,7 @@
 }
 
 /*-----------------------------------------------------------------------------
-DIMM-independant configuration functions.
+DIMM-independent configuration functions.
 -----------------------------------------------------------------------------*/
 
 struct dimm_size {
@@ -206,7 +206,7 @@
 	}
 
 	/* SPD byte 31 is the memory size divided by 4 so we
-	 * need to muliply by 4 to get the total size.
+	 * need to multiply by 4 to get the total size.
 	 */
 	sz.side1 *= 4;
 	sz.side2 *= 4;
@@ -426,12 +426,12 @@
 	u16 value;
 	int igd_memory = 0;
 
-	printk(BIOS_DEBUG, "Setting initial Nothbridge registers....\n");
+	printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n");
 
 	/* Set the value for Fixed DRAM Hole Control Register */
 	pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
 
-	/* Set the value for Programable Attribute Map Registers
+	/* Set the value for Programmable Attribute Map Registers
 	 * Ideally, this should be R/W for as many ranges as possible.
 	 */
 	pci_write_config8(NORTHBRIDGE, PAM0, 0x30);
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 43400ab..3fd5765 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -484,7 +484,7 @@
 }
 
 /*-----------------------------------------------------------------------------
-DIMM-independant configuration functions:
+DIMM-independent configuration functions:
 -----------------------------------------------------------------------------*/
 
 /**
@@ -588,7 +588,7 @@
 		tRCD = spd_read_byte(dimm, SPD_tRCD);
 		tRP = spd_read_byte(dimm, SPD_tRP);
 		if (tRCD != tRP) {
-			PRINTK_DEBUG(" Disabling RAS lockouk due to tRCD (%d) != tRP (%d)\n", tRCD, tRP);
+			PRINTK_DEBUG(" Disabling RAS lockout due to tRCD (%d) != tRP (%d)\n", tRCD, tRP);
 			controller_mode &= ~(1 << 15);
 		}
 
@@ -746,7 +746,7 @@
 
 	/* FIXME: guess work starts here...
 	 *
-	 * Intel refers to DQ turn-arround values for back to calculate the values,
+	 * Intel refers to DQ turn-around values for back to calculate the values,
 	 * but i have no idea what this means
 	 */
 
@@ -900,7 +900,7 @@
 	/* Set the value for Fixed DRAM Hole Control Register */
 	pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
 
-	/* Set the value for Programable Attribute Map Registers
+	/* Set the value for Programmable Attribute Map Registers
 	 * Ideally, this should be R/W for as many ranges as possible.
 	 */
 	pci_write_config8(NORTHBRIDGE, PAM0, 0x30);
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 8c41cb8..16ae55f 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -574,7 +574,7 @@
 
 	MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) );
 
-	/* Initialze PEG_CAP */
+	/* Initialize PEG_CAP */
 	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2);
 	reg16 |= (1 << 8);
 	pci_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16);
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index bb0bb73..e3ff478 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -612,7 +612,7 @@
 			);
 
 		int err;
-		/* probe if VGA is connected and alway run */
+		/* probe if VGA is connected and always run */
 		/* VGA init if no LVDS is connected */
 		if (!probe_edid(mmiobase, 3) || probe_edid(mmiobase, 2))
 			err = intel_gma_init_vga(conf,
@@ -640,7 +640,7 @@
 }
 
 /* This doesn't reclaim stolen UMA memory, but IGD could still
-   be reenabled later. */
+   be re-enabled later. */
 static void gma_func0_disable(struct device *dev)
 {
 	struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0));
@@ -660,7 +660,7 @@
 	u32 reg32;
 	u8 val;
 
-	/* IGD needs to be Bus Master, also enable IO accesss */
+	/* IGD needs to be Bus Master, also enable IO access */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 |
 			PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index dbd5d42..ca800f7 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1432,7 +1432,7 @@
 	/* Don't die here, I have not come across any of these to test what
 	 * actually happens.
 	 */
-	printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
+	printk(BIOS_ERR, "Asymmetric DIMMs are not supported by this chipset\n");
 
 	sz.side2 -= (rows & 0x0f);		/* Subtract out rows on side 1 */
 	sz.side2 += ((rows >> 4) & 0x0f);	/* Add in rows on side 2 */
@@ -1931,8 +1931,8 @@
 		reg32 |= (1 << 2);
 	} else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
 			SYSINFO_DIMM_NOT_POPULATED) {
-		/* Dual Channel Assymetric */
-		printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
+		/* Dual Channel Asymmetric */
+		printk(BIOS_DEBUG, "Dual Channel Asymmetric.\n");
 		reg32 |= (1 << 0);
 	} else {
 		/* All bits 0 means Single Channel 0 operation */
@@ -2365,7 +2365,7 @@
 
 	if (sdram_capabilities_enhanced_addressing_xor()) {
 		if (!sysinfo->interleaved) {
-			/* Single Channel & Dual Channel Assymetric */
+			/* Single Channel & Dual Channel Asymmetric */
 			if (chan0_populated) {
 				if (chan0_dualsided) {
 					chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
@@ -2396,7 +2396,7 @@
 		}
 	} else {
 		if (!sysinfo->interleaved) {
-			/* Single Channel & Dual Channel Assymetric */
+			/* Single Channel & Dual Channel Asymmetric */
 			if (chan0_populated) {
 				if (chan0_dualsided) {
 					chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index 46d867f..33e8eaa 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -254,14 +254,14 @@
 
 /* some vga option roms are used for several chipsets but they only have one
  * PCI ID in their header. If we encounter such an option rom, we need to do
- * the mapping ourselfes
+ * the mapping ourselves
  */
 
 u32 map_oprom_vendev(u32 vendev)
 {
 	u32 new_vendev = vendev;
 
-	/* none curently. */
+	/* none currently. */
 
 	return new_vendev;
 }
@@ -758,7 +758,7 @@
 			u32 current_delta;
 
 			denom = candn * candp1 * 7;
-			/* Doesnt overflow for up to
+			/* Doesn't overflow for up to
 			   5000000 kHz = 5 GHz. */
 			m = (target_frequency * denom + 60000) / 120000;
 
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 381bfbd..f20ef2d 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -119,7 +119,7 @@
 	unsigned int	page_size; /* of whole DIMM in Bytes (4096 or 8192) */
 	unsigned int	banks;
 	unsigned int	ranks;
-	unsigned int	rank_capacity_mb; /* per rank in Mega Bytes */
+	unsigned int	rank_capacity_mb; /* per rank in Megabytes */
 } dimminfo_t;
 
 /* The setup is one DIMM per channel, so there's no need to find a
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 0d1696d..cc6d0d9 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -15,7 +15,7 @@
  */
 
 /* Please don't remove this. It's needed it to do debugging
-   and reverse engineering to support in futur more nehalem variants.  */
+   and reverse engineering to support in future more nehalem variants.  */
 #ifndef REAL
 #define REAL 1
 #endif
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index 36f0c3c..a2cda84 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -184,7 +184,7 @@
 	unsigned int	tRP;
 	unsigned int	tRCD;
 	unsigned int	tRAS;
-	unsigned int	rank_capacity_mb; /* per rank in Mega Bytes */
+	unsigned int	rank_capacity_mb; /* per rank in Megabytes */
 	u8		spd_data[256];
 };
 
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 1f52511..290d066 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -249,7 +249,7 @@
 
 /* some vga option roms are used for several chipsets but they only have one
  * PCI ID in their header. If we encounter such an option rom, we need to do
- * the mapping ourselfes
+ * the mapping ourselves
  */
 
 u32 map_oprom_vendev(u32 vendev)
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index 489dbc7..bcdeaa0 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -252,7 +252,7 @@
 			u32 current_delta;
 
 			denom = candn * candp1 * 7;
-			/* Doesnt overflow for up to
+			/* Doesn't overflow for up to
 			   5000000 kHz = 5 GHz.  */
 			m = (target_frequency * denom + 60000) / 120000;
 
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index df1e8a8..e39e6bc 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -237,7 +237,7 @@
 			u32 current_delta;
 
 			denom = candn * candp1 * 7;
-			/* Doesnt overflow for up to
+			/* Doesn't overflow for up to
 			   5000000 kHz = 5 GHz.  */
 			m = (target_frequency * denom + 60000) / 120000;
 
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index f3a1ba5..d06e929 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -71,7 +71,7 @@
  *
  * DEFAULT_MCHBAR + 0x4230 + 0x400 * X + 4 * Y: idle register
  *  Controls the idle time after issuing this DRAM command
- *  Bit 16-32: number of clock-cylces to idle
+ *  Bit 16-32: number of clock-cycles to idle
  *
  * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue
  *  Starts to execute all queued commands
@@ -835,7 +835,7 @@
 			die ("No lock frequency found");
 		}
 
-		/* Frequency mulitplier.  */
+		/* Frequency multiplier.  */
 		u32 FRQ = get_FRQ(ctrl->tCK);
 
 		/* The PLL will never lock if the required frequency is
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index a2ca1c1..738e285 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -72,7 +72,7 @@
 	/* Initialize superio */
 	mainboard_config_superio();
 
-	/* USB is inited in MRC if MRC is used.  */
+	/* USB is initialized in MRC if MRC is used.  */
 	if (CONFIG_USE_NATIVE_RAMINIT) {
 		early_usb_init(mainboard_usb_ports);
 	}
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index fbd6191..b3ee34a 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -810,7 +810,7 @@
 			die("Unhandled case\n");
 		}
 
-		//reg8 = 0x00; // FIXME dont switch on all clocks anyway
+		//reg8 = 0x00; // FIXME don't switch on all clocks anyway
 
 		MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0) & ~0x3f000000) |
 			((u32)(reg8 << 24));
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index aa5db7d..3f5c9c7 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -261,7 +261,7 @@
 	unsigned int	tRP;
 	unsigned int	tRCD;
 	unsigned int	tRAS;
-	unsigned int	rank_capacity_mb; /* per rank in Mega Bytes */
+	unsigned int	rank_capacity_mb; /* per rank in Megabytes */
 	u8		spd_data[256];
 };