diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 8c41cb8..16ae55f 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -574,7 +574,7 @@
 
 	MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) );
 
-	/* Initialze PEG_CAP */
+	/* Initialize PEG_CAP */
 	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2);
 	reg16 |= (1 << 8);
 	pci_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16);
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index bb0bb73..e3ff478 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -612,7 +612,7 @@
 			);
 
 		int err;
-		/* probe if VGA is connected and alway run */
+		/* probe if VGA is connected and always run */
 		/* VGA init if no LVDS is connected */
 		if (!probe_edid(mmiobase, 3) || probe_edid(mmiobase, 2))
 			err = intel_gma_init_vga(conf,
@@ -640,7 +640,7 @@
 }
 
 /* This doesn't reclaim stolen UMA memory, but IGD could still
-   be reenabled later. */
+   be re-enabled later. */
 static void gma_func0_disable(struct device *dev)
 {
 	struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0));
@@ -660,7 +660,7 @@
 	u32 reg32;
 	u8 val;
 
-	/* IGD needs to be Bus Master, also enable IO accesss */
+	/* IGD needs to be Bus Master, also enable IO access */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	pci_write_config32(dev, PCI_COMMAND, reg32 |
 			PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index dbd5d42..ca800f7 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1432,7 +1432,7 @@
 	/* Don't die here, I have not come across any of these to test what
 	 * actually happens.
 	 */
-	printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
+	printk(BIOS_ERR, "Asymmetric DIMMs are not supported by this chipset\n");
 
 	sz.side2 -= (rows & 0x0f);		/* Subtract out rows on side 1 */
 	sz.side2 += ((rows >> 4) & 0x0f);	/* Add in rows on side 2 */
@@ -1931,8 +1931,8 @@
 		reg32 |= (1 << 2);
 	} else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
 			SYSINFO_DIMM_NOT_POPULATED) {
-		/* Dual Channel Assymetric */
-		printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
+		/* Dual Channel Asymmetric */
+		printk(BIOS_DEBUG, "Dual Channel Asymmetric.\n");
 		reg32 |= (1 << 0);
 	} else {
 		/* All bits 0 means Single Channel 0 operation */
@@ -2365,7 +2365,7 @@
 
 	if (sdram_capabilities_enhanced_addressing_xor()) {
 		if (!sysinfo->interleaved) {
-			/* Single Channel & Dual Channel Assymetric */
+			/* Single Channel & Dual Channel Asymmetric */
 			if (chan0_populated) {
 				if (chan0_dualsided) {
 					chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
@@ -2396,7 +2396,7 @@
 		}
 	} else {
 		if (!sysinfo->interleaved) {
-			/* Single Channel & Dual Channel Assymetric */
+			/* Single Channel & Dual Channel Asymmetric */
 			if (chan0_populated) {
 				if (chan0_dualsided) {
 					chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;