soc/intel/common/block/fast_spi: Clean up header
Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex
values and rename BIOS_CONTROL macros, as the register is not in SPIBAR.
Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index e4483e1..58e3ca2 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -42,16 +42,16 @@
const pci_devfn_t dev = PCH_DEV_SPI;
uint8_t bios_cntl;
- bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
+ bios_cntl = pci_read_config8(dev, SPI_BIOS_CONTROL);
/* Disable the BIOS write protect so write commands are allowed. */
- bios_cntl &= ~SPIBAR_BIOS_CONTROL_EISS;
- bios_cntl |= SPIBAR_BIOS_CONTROL_WPD;
+ bios_cntl &= ~SPI_BIOS_CONTROL_EISS;
+ bios_cntl |= SPI_BIOS_CONTROL_WPD;
/* Enable Prefetching and caching. */
- bios_cntl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
- bios_cntl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
+ bios_cntl |= SPI_BIOS_CONTROL_PREFETCH_ENABLE;
+ bios_cntl &= ~SPI_BIOS_CONTROL_CACHE_DISABLE;
- pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);
+ pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl);
}
/*
@@ -63,9 +63,9 @@
uint32_t bc_cntl;
assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
- bc_cntl = pci_read_config32(dev, SPIBAR_BIOS_CONTROL);
+ bc_cntl = pci_read_config32(dev, SPI_BIOS_CONTROL);
bc_cntl |= bios_cntl_bit;
- pci_write_config32(dev, SPIBAR_BIOS_CONTROL, bc_cntl);
+ pci_write_config32(dev, SPI_BIOS_CONTROL, bc_cntl);
}
/*
@@ -81,9 +81,9 @@
*/
void fast_spi_set_bios_interface_lock_down(void)
{
- fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_BILD);
+ fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_BILD);
- fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
+ fast_spi_read_post_write(SPI_BIOS_CONTROL);
}
/*
@@ -91,9 +91,9 @@
*/
void fast_spi_set_lock_enable(void)
{
- fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_LOCK_ENABLE);
+ fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_LOCK_ENABLE);
- fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
+ fast_spi_read_post_write(SPI_BIOS_CONTROL);
}
/*
@@ -104,9 +104,9 @@
if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW))
return;
- fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE);
+ fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE);
- fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
+ fast_spi_read_post_write(SPI_BIOS_CONTROL);
}
/*
@@ -114,9 +114,9 @@
*/
void fast_spi_set_eiss(void)
{
- fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EISS);
+ fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_EISS);
- fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
+ fast_spi_read_post_write(SPI_BIOS_CONTROL);
}
/*
@@ -348,10 +348,10 @@
(bios_region_top - 16MiB - MIN(extended_window_size, bios_size - 16MiB))
to (bios_region_top - 16MiB).
*/
- pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(16 * MiB));
+ pci_or_config32(dev, SPI_BIOS_CONTROL, SPI_BIOS_CONTROL_EXT_BIOS_LIMIT(16 * MiB));
/* Program EXT_BIOS EN */
- pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE);
+ pci_or_config32(dev, SPI_BIOS_CONTROL, SPI_BIOS_CONTROL_EXT_BIOS_ENABLE);
}
/*
@@ -390,8 +390,8 @@
/* Read SPI Write Protect disable status. */
bool fast_spi_wpd_status(void)
{
- return pci_read_config16(PCH_DEV_SPI, SPIBAR_BIOS_CONTROL) &
- SPIBAR_BIOS_CONTROL_WPD;
+ return pci_read_config16(PCH_DEV_SPI, SPI_BIOS_CONTROL) &
+ SPI_BIOS_CONTROL_WPD;
}
/* Enable SPI Write Protect. */
@@ -400,7 +400,7 @@
const pci_devfn_t dev = PCH_DEV_SPI;
uint8_t bios_cntl;
- bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
- bios_cntl &= ~SPIBAR_BIOS_CONTROL_WPD;
- pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);
+ bios_cntl = pci_read_config8(dev, SPI_BIOS_CONTROL);
+ bios_cntl &= ~SPI_BIOS_CONTROL_WPD;
+ pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl);
}
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
index 6ec12da..945feb0 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
@@ -5,22 +5,21 @@
/* PCI configuration registers */
-#define SPIDVID_OFFSET 0x0
-#define SPIBAR_BIOS_CONTROL 0xdc
+#define SPI_BIOS_CONTROL 0xdc
/* Extended Bios Support Registers */
#define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */
/* Bit definitions for BIOS_CONTROL */
-#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)
-#define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1)
-#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE (1 << 28)
-#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2)
-#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3)
-#define SPIBAR_BIOS_CONTROL_EISS (1 << 5)
-#define SPIBAR_BIOS_CONTROL_BILD (1 << 7)
-#define SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE (1 << 27)
-#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff))
+#define SPI_BIOS_CONTROL_WPD (1 << 0)
+#define SPI_BIOS_CONTROL_LOCK_ENABLE (1 << 1)
+#define SPI_BIOS_CONTROL_CACHE_DISABLE (1 << 2)
+#define SPI_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3)
+#define SPI_BIOS_CONTROL_EISS (1 << 5)
+#define SPI_BIOS_CONTROL_BILD (1 << 7)
+#define SPI_BIOS_CONTROL_EXT_BIOS_ENABLE (1 << 27)
+#define SPI_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE (1 << 28)
+#define SPI_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff))
/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
@@ -30,29 +29,29 @@
#define SPIBAR_DLOCK 0x0c
#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4)
#define SPIBAR_FPR_BASE 0x84
-#define SPIBAR_FPR(n) 0x84 + (4 * n))
-#define SPIBAR_PREOP 0xA4
-#define SPIBAR_OPTYPE 0xA6
-#define SPIBAR_OPMENU_LOWER 0xA8
-#define SPIBAR_OPMENU_UPPER 0xAc
-#define SPIBAR_FDOC 0xB4
-#define SPIBAR_FDOD 0xB8
+#define SPIBAR_FPR(n) (0x84 + (4 * (n)))
+#define SPIBAR_PREOP 0xa4
+#define SPIBAR_OPTYPE 0xa6
+#define SPIBAR_OPMENU_LOWER 0xa8
+#define SPIBAR_OPMENU_UPPER 0xac
+#define SPIBAR_FDOC 0xb4
+#define SPIBAR_FDOD 0xb8
#define SPIBAR_PTINX 0xcc
#define SPIBAR_PTDATA 0xd0
/* Bit definitions for BFPREG (0x00) register */
-#define SPIBAR_BFPREG_PRB_MASK (0x7fff)
-#define SPIBAR_BFPREG_PRL_SHIFT (16)
+#define SPIBAR_BFPREG_PRB_MASK 0x7fff
+#define SPIBAR_BFPREG_PRL_SHIFT 16
#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
#define SPIBAR_BFPREG_SBRS (1 << 31)
/* Bit definitions for HSFSTS_CTL (0x04) register */
-#define SPIBAR_HSFSTS_FDBC_MASK (0x3f << 24)
+#define SPIBAR_HSFSTS_FDBC_MASK (0x3f << 24)
#define SPIBAR_HSFSTS_FDBC(n) (((n) << 24) & SPIBAR_HSFSTS_FDBC_MASK)
#define SPIBAR_HSFSTS_WET (1 << 21)
#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17)
-#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) \
- & SPIBAR_HSFSTS_FCYCLE_MASK)
+#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK)
+
/* Supported flash cycle types */
#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0)
#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2)
@@ -74,12 +73,12 @@
#define SPIBAR_HSFSTS_AEL (1 << 2)
#define SPIBAR_HSFSTS_FCERR (1 << 1)
#define SPIBAR_HSFSTS_FDONE (1 << 0)
-#define SPIBAR_HSFSTS_W1C_BITS (0xff)
+#define SPIBAR_HSFSTS_W1C_BITS 0xff
/* Bit definitions for FADDR (0x08) register */
-#define SPIBAR_FADDR_MASK 0x7FFFFFF
+#define SPIBAR_FADDR_MASK 0x7ffffff
-/* Bit definitions for DLOCK (0x0C) register */
+/* Bit definitions for DLOCK (0x0c) register */
#define SPIBAR_DLOCK_PR0LOCKDN (1 << 8)
#define SPIBAR_DLOCK_PR1LOCKDN (1 << 9)
#define SPIBAR_DLOCK_PR2LOCKDN (1 << 10)
@@ -89,12 +88,12 @@
/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
#define SPIBAR_FDATA_FIFO_SIZE 0x40
-/* Bit definitions for FDOC (0xB4) register */
+/* Bit definitions for FDOC (0xb4) register */
#define SPIBAR_FDOC_COMPONENT (1 << 12)
#define SPIBAR_FDOC_FDSI_1 (1 << 2)
/* Flash Descriptor Component Section - Component 0 Density Bit Settings */
-#define FLCOMP_C0DEN_MASK 0xF
+#define FLCOMP_C0DEN_MASK 0xf
#define FLCOMP_C0DEN_8MB 4
#define FLCOMP_C0DEN_16MB 5
#define FLCOMP_C0DEN_32MB 6
@@ -103,7 +102,7 @@
#define SPIBAR_FPR_WPE (1 << 31) /* Flash Write protected */
#define SPIBAR_FPR_MAX 5
-/* Programmable values for OPMENU_LOWER(0xA8) & OPMENU_UPPER(0xAC) register */
+/* Programmable values for OPMENU_LOWER(0xa8) & OPMENU_UPPER(0xac) register */
#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
#define SPI_OPTYPE_0 0x01 /* Write, no address */
#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
@@ -130,7 +129,7 @@
(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
-/* Bit definitions for PTINX (0xCC) register */
+/* Bit definitions for PTINX (0xcc) register */
#define SPIBAR_PTINX_COMP_0 (0 << 14)
#define SPIBAR_PTINX_COMP_1 (1 << 14)
#define SPIBAR_PTINX_HORD_SFDP (0 << 12)
@@ -139,9 +138,9 @@
#define SPIBAR_PTINX_IDX_MASK 0xffc
/* Register Offsets of BIOS Flash Program Registers */
-#define SPIBAR_RESET_LOCK 0xF0
-#define SPIBAR_RESET_CTRL 0xF4
-#define SPIBAR_RESET_DATA 0xF8
+#define SPIBAR_RESET_LOCK 0xf0
+#define SPIBAR_RESET_CTRL 0xf4
+#define SPIBAR_RESET_DATA 0xf8
/* Programmable values of Bit0 (SSL) of Set STRAP MSG LOCK (0xF0) Register */
#define SPIBAR_RESET_LOCK_DISABLE 0 /* Set_Strap Lock(SSL) Bit 0 = 0 */
@@ -150,7 +149,7 @@
/* Programmable values of Bit0(SSMS) of Set STRAP MSG Control (0xF4) Register*/
#define SPIBAR_RESET_CTRL_SSMC 1 /* Set_Strap Mux Select(SSMS) Bit=1*/
-#define SPIBAR_HWSEQ_XFER_TIMEOUT 5000 /* max 5s*/
+#define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000
void *fast_spi_get_bar(void);
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
index 59ad7b4..1b0652d 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
@@ -110,7 +110,7 @@
struct stopwatch sw;
uint32_t hsfsts;
- stopwatch_init_msecs_expire(&sw, SPIBAR_HWSEQ_XFER_TIMEOUT);
+ stopwatch_init_msecs_expire(&sw, SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
do {
hsfsts = fast_spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
@@ -125,7 +125,7 @@
} while (!(stopwatch_expired(&sw)));
printk(BIOS_ERR, "SPI Transaction Timeout (Exceeded %d ms) at Flash Offset %x HSFSTS = 0x%08x\n",
- SPIBAR_HWSEQ_XFER_TIMEOUT, flash_addr, hsfsts);
+ SPIBAR_HWSEQ_XFER_TIMEOUT_MS, flash_addr, hsfsts);
return E_TIMEOUT;
}