Replace some ENV_ROMSTAGE with ENV_RAMINIT
With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.
Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c
index 5f52ca0..97345d9 100644
--- a/src/drivers/amd/agesa/def_callouts.c
+++ b/src/drivers/amd/agesa/def_callouts.c
@@ -129,7 +129,7 @@
AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
- if (!ENV_ROMSTAGE)
+ if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED;
return AmdMemoryReadSPD (Func, Data, ConfigPtr);
@@ -139,7 +139,7 @@
{
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- if (!ENV_ROMSTAGE)
+ if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED;
if (info->MemChannelId > 0)
diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c
index 31db0b6..db53a3c 100644
--- a/src/drivers/amd/agesa/state_machine.c
+++ b/src/drivers/amd/agesa/state_machine.c
@@ -18,7 +18,7 @@
#include "Dispatcher.h"
#endif
-#if ENV_ROMSTAGE
+#if ENV_RAMINIT
#include <PlatformMemoryConfiguration.h>
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END};
#endif
@@ -262,7 +262,7 @@
if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_entry_id)
timestamp_add_now(task.ts_entry_id);
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
final = romstage_dispatch(cb, func, StdHeader);
if (ENV_RAMSTAGE)
diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c
index e166cf7..6ea3aa3 100644
--- a/src/drivers/intel/fsp2_0/hand_off_block.c
+++ b/src/drivers/intel/fsp2_0/hand_off_block.c
@@ -115,7 +115,7 @@
{
uint32_t *list_loc;
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
return fsp_hob_list_ptr;
list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME);
return (list_loc) ? (void *)(uintptr_t)(*list_loc) : NULL;
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
index 2537b38..629f331 100644
--- a/src/drivers/intel/fsp2_0/util.c
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -77,7 +77,7 @@
return CB_ERR;
}
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
soc_validate_fspm_header(hdr);
return CB_SUCCESS;
@@ -118,7 +118,7 @@
static inline bool fspm_env(void)
{
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
return true;
return false;
}
diff --git a/src/include/rules.h b/src/include/rules.h
index 4bcd8ea..b2f2142 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -294,6 +294,7 @@
#define ENV_CREATES_CBMEM ENV_ROMSTAGE
#define ENV_HAS_CBMEM (ENV_ROMSTAGE | ENV_POSTCAR | ENV_RAMSTAGE)
+#define ENV_RAMINIT ENV_ROMSTAGE
#if ENV_X86
#define ENV_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index f8112d6..e1334f4 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -106,7 +106,7 @@
static inline bool fspm_env(void)
{
/* FSP-M is assumed to be loaded in romstage. */
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
return true;
return false;
}
diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
index 518bc95..432f104 100644
--- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
@@ -180,7 +180,7 @@
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
u8 index;
- if (!ENV_ROMSTAGE)
+ if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED;
if (CONFIG(BAP_E20_DDR3_1066))
diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c
index e80cc12..b06b2cf 100644
--- a/src/mainboard/lippert/frontrunner-af/sema.c
+++ b/src/mainboard/lippert/frontrunner-af/sema.c
@@ -53,7 +53,7 @@
char one_spd_byte;
/* Fake read just to setup SMBUS controller. */
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
smbus_readSpd(0xa0, &one_spd_byte, 1);
/* Notify the SMC we're alive and kicking, or after a while it will
diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c
index 4944a85..aff72ca 100644
--- a/src/mainboard/pcengines/apu1/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c
@@ -38,7 +38,7 @@
{
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- if (!ENV_ROMSTAGE)
+ if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED;
u8 index = get_spd_offset();
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index d17dc366..efd88d8 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -107,7 +107,7 @@
{
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- if (!ENV_ROMSTAGE)
+ if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED;
u8 index = get_spd_offset();
diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c
index c5e6cac..4085855 100644
--- a/src/soc/amd/common/pi/agesawrapper.c
+++ b/src/soc/amd/common/pi/agesawrapper.c
@@ -68,7 +68,7 @@
aip->NewStructPtr = buf;
aip->NewStructSize = len;
} else {
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
aip->AllocationMethod = PreMemHeap;
if (ENV_RAMSTAGE)
aip->AllocationMethod = PostMemDram;
@@ -412,7 +412,7 @@
StdHeader = aip->NewStructPtr;
StdHeader->Func = func;
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
status = romstage_dispatch(StdHeader);
if (ENV_RAMSTAGE)
status = ramstage_dispatch(StdHeader);
diff --git a/src/soc/amd/common/pi/def_callouts.c b/src/soc/amd/common/pi/def_callouts.c
index 414de6f..223abe3 100644
--- a/src/soc/amd/common/pi/def_callouts.c
+++ b/src/soc/amd/common/pi/def_callouts.c
@@ -23,7 +23,7 @@
#else
const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
/* Required callouts */
-#if ENV_ROMSTAGE
+#if ENV_RAMINIT
{ AGESA_HALT_THIS_AP, agesa_HaltThisAp },
#endif
{ AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c
index ba0f0ee..b94f3a6 100644
--- a/src/soc/amd/stoneyridge/BiosCallOuts.c
+++ b/src/soc/amd/stoneyridge/BiosCallOuts.c
@@ -86,7 +86,7 @@
DEVTREE_CONST struct soc_amd_stoneyridge_config *conf;
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
- if (!ENV_ROMSTAGE)
+ if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED;
dev = pcidev_path_on_root(DCT_DEVFN);
diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c
index 080adc0..cdfa0f7 100644
--- a/src/soc/cavium/cn81xx/sdram.c
+++ b/src/soc/cavium/cn81xx/sdram.c
@@ -29,7 +29,7 @@
#define BDK_RNM_CTL_STATUS 0
#define BDK_RNM_RANDOM 0x100000
-#if ENV_ROMSTAGE
+#if ENV_RAMINIT
/* Enable RNG for DRAM init */
static void rnm_init(void)
{
diff --git a/src/soc/mediatek/mt8186/emi.c b/src/soc/mediatek/mt8186/emi.c
index 6e25441..4f300da 100644
--- a/src/soc/mediatek/mt8186/emi.c
+++ b/src/soc/mediatek/mt8186/emi.c
@@ -15,7 +15,7 @@
const struct mem_chip_info *mc;
size_t size = 0;
- if (ENV_ROMSTAGE) {
+ if (ENV_RAMINIT) {
size = mtk_dram_size();
printk(BIOS_INFO, "dram size (romstage): %#lx\n", size);
return size;
diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c
index 977f938..a8badde 100644
--- a/src/soc/sifive/fu540/clock.c
+++ b/src/soc/sifive/fu540/clock.c
@@ -56,7 +56,7 @@
#define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)
/* Clock initialization should only be done in romstage. */
-#if ENV_ROMSTAGE
+#if ENV_RAMINIT
struct pll_settings {
unsigned int divr:6;
unsigned int divf:9;
@@ -247,7 +247,7 @@
asm volatile ("fence");
}
-#endif /* ENV_ROMSTAGE */
+#endif /* ENV_RAMINIT */
/* Get the core clock's frequency, in KHz */
int clock_get_coreclk_khz(void)
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 6ed3dce..bbbc5e6 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -310,6 +310,6 @@
setup_pch_gpios(&mainboard_gpio_map);
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
enable_smbus();
}
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index 4647bf1..3a0e0b1 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -57,7 +57,7 @@
#define TCO_BASE 0x60
-#if ENV_ROMSTAGE
+#if ENV_RAMINIT
void i82801gx_early_init(void)
{
enable_smbus();
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index f781098..b8bc9d8 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -47,7 +47,7 @@
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
enable_smbus();
/* Set up RCBA. */
diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c
index 327c8fc..f7e880c 100644
--- a/src/southbridge/intel/i82801jx/early_init.c
+++ b/src/southbridge/intel/i82801jx/early_init.c
@@ -69,7 +69,7 @@
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
- if (ENV_ROMSTAGE)
+ if (ENV_RAMINIT)
enable_smbus();
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
index b1a346a..3302574 100644
--- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
+++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
@@ -2,7 +2,7 @@
#define AGESA_ENTRY_CFG_H
-#if ENV_ROMSTAGE
+#if ENV_RAMINIT
#define AGESA_ENTRY_INIT_RESET TRUE
#define AGESA_ENTRY_INIT_EARLY TRUE