nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMIC
Change-Id: I4ec59cea256a39a94b05cdeb8f914830ac0bd3f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index e3f9aec..5b92842 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -25,6 +25,9 @@
binary is used meaning a jump is made from RW to the RO region
and back to the RW region after the binary is done.
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index c00c801..501caf1 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -14,7 +14,6 @@
#include <boot/tables.h>
#include <security/intel/txt/txt_register.h>
#include <southbridge/intel/lynxpoint/pch.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include "chip.h"
#include "haswell.h"
@@ -336,9 +335,6 @@
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
- if (CONFIG(CHROMEOS_RAMOOPS))
- chromeos_reserve_ram_oops(dev, index++);
-
*resource_cnt = index;
}
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 215560f..e06bdac 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -32,6 +32,9 @@
binary is used meaning a jump is made from RW to the RO region
and back to the RW region after the binary is done.
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index ead3c67..fbed687 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -14,7 +14,6 @@
#include "chip.h"
#include "sandybridge.h"
#include <cpu/intel/smm_reloc.h>
-#include <vendorcode/google/chromeos/chromeos.h>
/* IGD UMA memory */
static uint64_t uma_memory_base = 0;
@@ -68,9 +67,6 @@
reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
- if (CONFIG(CHROMEOS_RAMOOPS))
- chromeos_reserve_ram_oops(dev, index++);
-
if (is_sandybridge()) {
/* Required for SandyBridge sighting 3715511 */
bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 8811b38..f539be8 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -37,6 +37,9 @@
select CPU_INTEL_COMMON
select CPU_HAS_L2_ENABLE_MSR
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
index f4cbc94..e8f9768 100644
--- a/src/soc/intel/baytrail/northcluster.c
+++ b/src/soc/intel/baytrail/northcluster.c
@@ -10,7 +10,6 @@
#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
-#include <vendorcode/google/chromeos/chromeos.h>
/*
* Host Memory Map:
@@ -119,9 +118,6 @@
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
-
- if (CONFIG(CHROMEOS_RAMOOPS))
- chromeos_reserve_ram_oops(dev, index++);
}
static void nc_generate_ssdt(const struct device *dev)
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 0e1b6db..720597c 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -52,6 +52,9 @@
The amount of anticipated stack usage in CAR by bootblock and
other stages.
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 339e293..b7ddee4 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -13,7 +13,6 @@
#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#include <stddef.h>
/*
@@ -145,9 +144,6 @@
base_k = RES_IN_KiB(LAPIC_DEFAULT_BASE);
size_k = RES_IN_KiB(0x00100000);
mmio_resource(dev, index++, base_k, size_k);
-
- if (CONFIG(CHROMEOS_RAMOOPS))
- chromeos_reserve_ram_oops(dev, index++);
}
static void nc_generate_ssdt(const struct device *dev)