Remove various .c #includes from Intel 440BX/82371EB boards.
- Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c
into distinct compilation units, and don't #include the files anymore
in romstage.c files.
- Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and
northbridge/intel/i440bx/debug.c.
- Add various header files which are now needed.
- Make functions that need to be visible non-static.
- Drop a remaining "select ROMCC" from a 4440BX board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index 24892f2..816ef1b 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -25,4 +25,6 @@
driver-y += i82371eb_smbus.c
driver-y += i82371eb_reset.c
-#romstage-y += i82371eb_early_rom.c
+romstage-y += i82371eb_early_pm.c
+romstage-y += i82371eb_early_smbus.c
+
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 1093766..0536c54 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -21,10 +21,17 @@
#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
+#if !defined(ASSEMBLY)
#if !defined(__PRE_RAM__)
+
+#include <arch/io.h>
+#include <device/device.h>
#include "chip.h"
+
void i82371eb_enable(device_t dev);
void i82371eb_hard_reset(void);
+
+#endif
#endif
/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
@@ -55,6 +62,8 @@
#define PMBA 0x40 /* Power management base address */
#define PMREGMISC 0x80 /* Miscellaneous power management */
+#define PM_IO_BASE 0xe400
+
/* Bit definitions */
#define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */
#define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
index e6dd68e..ad5fe7c 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
@@ -19,24 +19,25 @@
*/
#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
#include <device/pci_ids.h>
+#include <console/console.h>
#include "i82371eb.h"
-#define PM_IO_BASE 0xe400
+void enable_pm(void);
-static void enable_pm(void)
+void enable_pm(void)
{
device_t dev;
u8 reg8;
u16 reg16;
- /* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */
+ /* Get the SMBus/PM device of the 82371AB/EB/MB. */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
- if (dev == PCI_DEV_INVALID)
- die("SMBus/PM controller not found\n");
-
/* Set the PM I/O base. */
pci_write_config32(dev, PMBA, PM_IO_BASE | 1);
@@ -50,4 +51,3 @@
reg8 |= PMIOSE;
pci_write_config8(dev, PMREGMISC, reg8);
}
-
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
index 76ae9f5..0ae5667 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
@@ -18,28 +18,29 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* TODO: Implement smbus_write_byte(), smbus_recv_byte(), smbus_send_byte(). */
-
#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci_def.h>
#include "i82371eb.h"
#include "i82371eb_smbus.h"
#define SMBUS_IO_BASE 0x0f00
-static void enable_smbus(void)
+int smbus_read_byte(u8 device, u8 address);
+
+void enable_smbus(void)
{
device_t dev;
u8 reg8;
u16 reg16;
- /* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */
+ /* Get the SMBus/PM device of the 82371AB/EB/MB. */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
- if (dev == PCI_DEV_INVALID)
- die("SMBus/PM controller not found\n");
-
/* Set the SMBus I/O base. */
pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
@@ -57,7 +58,7 @@
outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
}
-static int smbus_read_byte(u8 device, u8 address)
+int smbus_read_byte(u8 device, u8 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
index 1502570..3072b6c 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
@@ -24,6 +24,7 @@
#include <device/pci_ids.h>
#include <device/smbus.h>
#include "i82371eb.h"
+#include "i82371eb_smbus.h"
/* TODO: Needed later? */
static const struct smbus_bus_operations lops_smbus_bus = {
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/i82371eb_smbus.h
index a189425..54e7906 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.h
@@ -10,6 +10,9 @@
#define SMBUS_STATUS_MASK 0x1e
#define SMBUS_ERROR_FLAG (1<<2)
+void enable_smbus(void);
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address);
+
static inline void smbus_delay(void)
{
outb(0x80, 0x80);
@@ -63,7 +66,7 @@
return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
{
unsigned status_register;
unsigned byte;