commit 11334729c9aa3f09b3e01a491a2d007a0aea7201
author Angel Pons <th3fanbus@gmail.com> Mon Oct 05 16:34:03 2020 +0200
committer Philipp Deppenwiese <zaolin.daisuki@gmail.com> Thu Oct 15 08:31:48 2020 +0000
tree 148caff85c45ee443a1ba41a1d9ab24dd135902e
parent adcb870837518283fac6eac24a628d42912fd4a3

security/intel/txt: Use `smm_region()` to get TSEG base

This function is available for all TXT-capable platforms. Use it.
As it also provides the size of TSEG, display it when logging is on.

Change-Id: I4b3dcbc61854fbdd42275bf9456eaa5ce783e8aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/security/intel/txt/ramstage.c

diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c
index bc30da5..263bc9d 100644
--- a/src/security/intel/txt/ramstage.c
+++ b/src/security/intel/txt/ramstage.c
@@ -8,6 +8,7 @@
 #include <console/console.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <device/pci_ops.h>
 #include <types.h>
 
@@ -204,7 +205,11 @@
 static void lockdown_intel_txt(void *unused)
 {
 	const uint64_t status = read64((void *)TXT_SPAD);
-	uintptr_t tseg = 0;
+
+	uintptr_t tseg_base;
+	size_t tseg_size;
+
+	smm_region(&tseg_base, &tseg_size);
 
 	if (status & ACMSTS_TXT_DISABLED)
 		return;
@@ -232,7 +237,7 @@
 		union dpr_register dpr = {
 			.lock = 1,
 			.size = 3,
-			.top  = tseg,
+			.top  = tseg_base / MiB,
 		};
 		write64((void *)TXT_DPR, dpr.raw);
 
@@ -248,7 +253,7 @@
 	 */
 	write64((void *)TXT_HEAP_SIZE, 0xE0000);
 	write64((void *)TXT_HEAP_BASE,
-		ALIGN_DOWN((tseg * MiB) - read64((void *)TXT_HEAP_SIZE), 4096));
+		ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096));
 
 	/*
 	 * Document Number: 558294