baytrail: Configure MSR for 2-core and 4-core P-state configutation
Suggested settings to try for performace regression:
2-core systems:
- MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL)
- MSR_POWER_MISC clear bit 2,3
- \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL)
4-core systems:
- MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL)
- MSR_POWER_MISC clear bit 2,3
- \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL)
BUG=chrome-os-partner:26211
BRANCH=baytrail
TEST=emerge-rambi chromeos-coreboot-rambi
Change-Id: Ib68a86525204ae47a820c269257a7b8df9300a6a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192573
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 8c8c0be0000043610eaa56926eff978f352819b8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7213
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2 files changed