commit 1110b2f4620380e6fad6efce30a33bb6739df77b
author Angel Pons <th3fanbus@gmail.com> Tue Sep 15 00:03:35 2020 +0200
committer Patrick Georgi <pgeorgi@google.com> Mon Dec 07 15:24:20 2020 +0000
tree 47b1dc291b2125a73a50fb239f0c79fee611bb4d
parent 02a23b510ca4bc9eb4e78b427bc93c7bd564f401

nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}

There's no need to wrap these macros with casts. Removing them allows
dropping more casts in `early_init.c`.

To avoid binary changes the casts are put into the
{MCH,DMI,EP}BAR{8,16,32} macros instead where they are needed to reach
the right memory locations.

Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/ironlake/early_init.c

diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c
index fa89bd9..e0120fe 100644
--- a/src/northbridge/intel/ironlake/early_init.c
+++ b/src/northbridge/intel/ironlake/early_init.c
@@ -19,9 +19,9 @@
 	/* Set up all hardcoded northbridge BARs */
 	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0);
 
 	/* Set C0000-FFFFF to access RAM on both reads and writes */

src/northbridge/intel/ironlake/ironlake.h

diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 86c6054..8abc3fc 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -25,13 +25,8 @@
 #define IRONLAKE_SERVER		2
 
 /* Northbridge BARs */
-#ifndef __ACPI__
-#define DEFAULT_MCHBAR		((u8 *)0xfed10000)	/* 16 KB */
-#define DEFAULT_DMIBAR		((u8 *)0xfed18000)	/* 4 KB */
-#else
 #define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
 #define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
-#endif
 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
 
 #define QUICKPATH_BUS 0xff
@@ -100,9 +95,9 @@
  * MCHBAR
  */
 
-#define MCHBAR8(x)			(*((volatile u8  *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x)			(*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x)			(*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
+#define MCHBAR8(x)			(*((volatile u8  *)((u8 *)DEFAULT_MCHBAR + (x))))
+#define MCHBAR16(x)			(*((volatile u16 *)((u8 *)DEFAULT_MCHBAR + (x))))
+#define MCHBAR32(x)			(*((volatile u32 *)((u8 *)DEFAULT_MCHBAR + (x))))
 #define MCHBAR8_AND(x,  and)		(MCHBAR8(x)  = MCHBAR8(x)  & (and))
 #define MCHBAR16_AND(x, and)		(MCHBAR16(x) = MCHBAR16(x) & (and))
 #define MCHBAR32_AND(x, and)		(MCHBAR32(x) = MCHBAR32(x) & (and))
@@ -116,9 +111,9 @@
  * EPBAR - Egress Port Root Complex Register Block
  */
 
-#define EPBAR8(x)	(*((volatile u8  *)(DEFAULT_EPBAR + (x))))
-#define EPBAR16(x)	(*((volatile u16 *)(DEFAULT_EPBAR + (x))))
-#define EPBAR32(x)	(*((volatile u32 *)(DEFAULT_EPBAR + (x))))
+#define EPBAR8(x)	(*((volatile u8  *)((u8 *)DEFAULT_EPBAR + (x))))
+#define EPBAR16(x)	(*((volatile u16 *)((u8 *)DEFAULT_EPBAR + (x))))
+#define EPBAR32(x)	(*((volatile u32 *)((u8 *)DEFAULT_EPBAR + (x))))
 
 #include "registers/epbar.h"
 
@@ -126,9 +121,9 @@
  * DMIBAR
  */
 
-#define DMIBAR8(x)	(*((volatile u8  *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR16(x)	(*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR32(x)	(*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
+#define DMIBAR8(x)	(*((volatile u8  *)((u8 *)DEFAULT_DMIBAR + (x))))
+#define DMIBAR16(x)	(*((volatile u16 *)((u8 *)DEFAULT_DMIBAR + (x))))
+#define DMIBAR32(x)	(*((volatile u32 *)((u8 *)DEFAULT_DMIBAR + (x))))
 
 #include "registers/dmibar.h"