Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.
Side-effects to consider:
Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.
With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.
Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 2e46516..718d2b2 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -29,6 +29,7 @@
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "superio/smsc/kbc1100/kbc1100_early_init.c"
@@ -45,8 +46,8 @@
/* all cores: allow caching of flash chip code and data
* (there are no cache-as-ram reliability concerns with family 14h)
*/
- __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
- __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+ __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
+ __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
*/