Modify DMI init for IvyBridge
The ASPM setting for the Direct Media Interface should no longer be done on
Ivybridge/PantherPoint based systems.
Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: http://review.coreboot.org/969
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index e3334c4..b1f7c72 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -347,10 +347,12 @@
DMIBAR32(0x1d0) = 0xffffffff;
/* Steps prior to DMI ASPM */
- reg32 = DMIBAR32(0x250);
- reg32 &= ~((1 << 22)|(1 << 20));
- reg32 |= (1 << 21);
- DMIBAR32(0x250) = reg32;
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ reg32 = DMIBAR32(0x250);
+ reg32 &= ~((1 << 22)|(1 << 20));
+ reg32 |= (1 << 21);
+ DMIBAR32(0x250) = reg32;
+ }
reg32 = DMIBAR32(0x238);
reg32 |= (1 << 29);
@@ -372,9 +374,11 @@
}
/* Enable ASPM on SNB link, should happen before PCH link */
- reg32 = DMIBAR32(0xd04);
- reg32 |= (1 << 4);
- DMIBAR32(0xd04) = reg32;
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
+ reg32 = DMIBAR32(0xd04);
+ reg32 |= (1 << 4);
+ DMIBAR32(0xd04) = reg32;
+ }
reg32 = DMIBAR32(0x88);
reg32 |= (1 << 1) | (1 << 0);