soc/amd/picasso: add devicetree setting for PSPP policy
Since the default for the corresponding UPD of the Picasso FSP is
DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE,
add a deviectree setting for each board that's using the Picasso SoC
code to not change the setting for the existing boards.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 359fa95..4c43b1f 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -263,6 +263,13 @@
GPP_CLK_OFF, /* GPP clk off */
} gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
+ /* performance policy for the PCIe links: power consumption vs. link speed */
+ enum {
+ DXIO_PSPP_PERFORMANCE = 0,
+ DXIO_PSPP_BALANCED,
+ DXIO_PSPP_POWERSAVE,
+ } pspp_policy;
+
/* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
bool acp_i2s_use_external_48mhz_osc;
diff --git a/src/soc/amd/picasso/fsp_m_params.c b/src/soc/amd/picasso/fsp_m_params.c
index f196e48..3532fb2 100644
--- a/src/soc/amd/picasso/fsp_m_params.c
+++ b/src/soc/amd/picasso/fsp_m_params.c
@@ -112,5 +112,8 @@
mcfg->sata_enable = devtree_sata_dev_enabled();
mcfg->hdmi2_disable = config->hdmi2_disable;
+ /* PCIe power vs. speed */
+ mcfg->pspp_policy = config->pspp_policy;
+
mainboard_updm_update(mcfg);
}