tree 6e4097d2c711ce7f7559116deb266deb0364dfc3
parent 65cbbe77ac8200d391cdb423c756bc93aabb16cc
author Lijian Zhao <lijian.zhao@intel.com> 1525736441 -0700
committer Patrick Georgi <pgeorgi@google.com> 1526645996 +0000

intel/fsp: Update Cannonlake FSP header

Update Cannonlake FSP header to version 7.x.2E.50, the following changes
were made,
Memory Init UPD:
	1. Add GDXC configuration options.
	2. Remove some internal graphics memory selections.
	2. Remove Fixed mid option for SaGv.
	3. Add DualDimm per channel board type.
	4. Remove PEG IMR options.
Silicon Init UPD:
	1. Add CD clock selections of 675MHz.
	2. Remove Pcode PreWake/Rampup/RampDn time selections.
	3. Remove C3 state demotion/unDemotion selections.

BUG=None
TEST=Build and boot up on meowth platform.

Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/26148
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>