Move TPM code out of chromeos
This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.
Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig
index 2239f70..74e1edd 100644
--- a/src/mainboard/google/bolt/Kconfig
+++ b/src/mainboard/google/bolt/Kconfig
@@ -16,6 +16,7 @@
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select EXTERNAL_MRC_BLOB
select INTEL_INT15
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig
index 7472c06..b1a64ee 100644
--- a/src/mainboard/google/butterfly/Kconfig
+++ b/src/mainboard/google/butterfly/Kconfig
@@ -13,6 +13,7 @@
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig
index a8faaab..5b97259 100644
--- a/src/mainboard/google/falco/Kconfig
+++ b/src/mainboard/google/falco/Kconfig
@@ -17,6 +17,7 @@
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select EXTERNAL_MRC_BLOB
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index 316434f..0f70925 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -12,6 +12,7 @@
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_NATIVE_VGA_INIT
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index ca8c2bd..b345d5e 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -41,9 +41,7 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <tpm.h>
#include <cbfs.h>
#include <southbridge/intel/bd82x6x/chip.h>
@@ -246,8 +244,9 @@
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ if (CONFIG_LPC_TPM) {
+ init_tpm(boot_mode == 2);
+ }
+
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index 31062ed..37a8548 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -15,6 +15,7 @@
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select EXTERNAL_MRC_BLOB
select INTEL_INT15
select PHYSICAL_REC_SWITCH
diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig
index 07405c6..9cf390a 100644
--- a/src/mainboard/google/parrot/Kconfig
+++ b/src/mainboard/google/parrot/Kconfig
@@ -12,6 +12,7 @@
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index d0fab67..a947c48 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -39,10 +39,8 @@
#include <cpu/x86/msr.h>
#include <halt.h>
#include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
#include <cbfs.h>
+#include <tpm.h>
#include "ec/compal/ene932/ec.h"
static void pch_enable_lpc(void)
@@ -197,8 +195,8 @@
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ if (CONFIG_LPC_TPM) {
+ init_tpm(boot_mode == 2);
+ }
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig
index d6a208b..2c1560a 100644
--- a/src/mainboard/google/peppy/Kconfig
+++ b/src/mainboard/google/peppy/Kconfig
@@ -17,6 +17,7 @@
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select EXTERNAL_MRC_BLOB
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index 4c9e891..1130d11 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -12,6 +12,7 @@
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select ALWAYS_LOAD_OPROM
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig
index f655b29..06317e9 100644
--- a/src/mainboard/google/samus/Kconfig
+++ b/src/mainboard/google/samus/Kconfig
@@ -15,6 +15,7 @@
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select EXTERNAL_MRC_BLOB
select CHROMEOS_RAMOOPS_DYNAMIC
select INTEL_INT15
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig
index fd4cb2f..cfbce5e 100644
--- a/src/mainboard/google/slippy/Kconfig
+++ b/src/mainboard/google/slippy/Kconfig
@@ -16,6 +16,7 @@
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select EXTERNAL_MRC_BLOB
select INTEL_DP
select INTEL_DDI
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
index ec03d87..eca83da 100644
--- a/src/mainboard/google/stout/Kconfig
+++ b/src/mainboard/google/stout/Kconfig
@@ -13,6 +13,7 @@
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index ee6ca4f..31b61e2 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -40,9 +40,7 @@
#include <halt.h>
#include "gpio.h"
#include <bootmode.h>
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <tpm.h>
#include <cbfs.h>
#include <ec/quanta/it8518/ec.h>
#include "ec.h"
@@ -251,8 +249,8 @@
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ if (CONFIG_LPC_TPM) {
+ init_tpm(boot_mode == 2);
+ }
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig
index c3e3361..f916138 100644
--- a/src/mainboard/intel/baskingridge/Kconfig
+++ b/src/mainboard/intel/baskingridge/Kconfig
@@ -11,6 +11,7 @@
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index c9d5cf1..bcf498b 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -39,10 +39,8 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <halt.h>
+#include <tpm.h>
#include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
#define SIO_PORT 0x164e
@@ -255,8 +253,8 @@
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ if (CONFIG_LPC_TPM) {
+ init_tpm(boot_mode == 2);
+ }
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 5a064d1..b8f616a 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -9,6 +9,7 @@
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_INT15
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
index 7c9dce4..fed4610 100644
--- a/src/mainboard/samsung/lumpy/Kconfig
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -5,6 +5,7 @@
select SYSTEM_TYPE_LAPTOP
select BOARD_ROMSIZE_KB_8192
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select CPU_INTEL_SOCKET_RPGA989
select EC_SMSC_MEC1308
select HAVE_ACPI_RESUME
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 9b1a023..ce064bb 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -32,6 +32,7 @@
#include <cbmem.h>
#include <console/console.h>
#include <bootmode.h>
+#include <tpm.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <southbridge/intel/bd82x6x/pch.h>
@@ -45,9 +46,6 @@
#if CONFIG_DRIVERS_UART_8250IO
#include <superio/smsc/lpc47n207/lpc47n207.h>
#endif
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
static void pch_enable_lpc(void)
{
@@ -273,8 +271,8 @@
}
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ if (CONFIG_LPC_TPM) {
+ init_tpm(boot_mode == 2);
+ }
timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
index 1eda8eb..f749c39 100644
--- a/src/mainboard/samsung/stumpy/Kconfig
+++ b/src/mainboard/samsung/stumpy/Kconfig
@@ -4,6 +4,7 @@
def_bool y
select BOARD_ROMSIZE_KB_8192
select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
select CPU_INTEL_SOCKET_RPGA989
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 6506c80..161c8d1 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -41,13 +41,11 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <halt.h>
+#include <tpm.h>
#include "gpio.h"
#if CONFIG_DRIVERS_UART_8250IO
#include <superio/smsc/lpc47n207/lpc47n207.h>
#endif
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
/* Stumpy USB Reset Disable defined in cmos.layout */
#if CONFIG_USE_OPTION_TABLE
@@ -283,8 +281,8 @@
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
-#if CONFIG_CHROMEOS
- init_chromeos(boot_mode);
-#endif
+ if (CONFIG_LPC_TPM) {
+ init_tpm(boot_mode == 2);
+ }
timestamp_add_now(TS_END_ROMSTAGE);
}