diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 998f887..0f0890a 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -45,7 +45,7 @@
 #include "northbridge/intel/haswell/raminit.h"
 #include "southbridge/intel/lynxpoint/pch.h"
 #include "southbridge/intel/lynxpoint/me.h"
-
+#include <tpm.h>
 
 static inline void reset_system(void)
 {
@@ -276,9 +276,9 @@
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
-	init_chromeos(boot_mode);
-#endif
+	if (CONFIG_LPC_TPM) {
+		init_tpm(wake_from_s3);
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }
 
diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig
index 942b6e5..fc9270b 100644
--- a/src/drivers/pc80/tpm/Kconfig
+++ b/src/drivers/pc80/tpm/Kconfig
@@ -1,5 +1,12 @@
+config MAINBOARD_HAS_LPC_TPM
+       bool
+       default n
+       help
+         Board has TPM support
+
 config LPC_TPM
-	bool
+	bool "Enable TPM support"
+	depends on MAINBOARD_HAS_LPC_TPM
 	default n
 	help
 	  Enable this option to enable LPC TPM support in coreboot.
@@ -15,3 +22,18 @@
 	  The default is specified by the TCG PC Client Specific TPM
 	  Interface Specification 1.2 and should not be changed unless
 	  the TPM being used does not conform to TPM TIS 1.2.
+
+config TPM_INIT_FAILURE_IS_FATAL
+	bool
+	default n
+	depends on LPC_TPM
+	help
+	  What to do if TPM init failed. If true, force a hard reset,
+	  otherwise just log error message to console.
+
+config SKIP_TPM_STARTUP_ON_NORMAL_BOOT
+	bool
+	default n
+	depends on LPC_TPM
+	help
+	  Skip TPM init on normal boot. Useful if payload does TPM init.
diff --git a/src/drivers/pc80/tpm/Makefile.inc b/src/drivers/pc80/tpm/Makefile.inc
index c900fe8..089d067 100644
--- a/src/drivers/pc80/tpm/Makefile.inc
+++ b/src/drivers/pc80/tpm/Makefile.inc
@@ -1,2 +1,3 @@
 romstage-$(CONFIG_LPC_TPM) += tpm.c
 ramstage-$(CONFIG_LPC_TPM) += tpm.c
+romstage-$(CONFIG_LPC_TPM) += romstage.c
diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/drivers/pc80/tpm/romstage.c
similarity index 91%
rename from src/vendorcode/google/chromeos/vboot.c
rename to src/drivers/pc80/tpm/romstage.c
index 6678aaa..5e29e3a 100644
--- a/src/vendorcode/google/chromeos/vboot.c
+++ b/src/drivers/pc80/tpm/romstage.c
@@ -23,10 +23,8 @@
 #include <arch/acpi.h>
 #include <tpm.h>
 #include <reset.h>
-#include "chromeos.h"
 
 //#define EXTRA_LOGGING
-#define UBOOT_DOES_TPM_STARTUP
 
 #define TPM_LARGE_ENOUGH_COMMAND_SIZE 256	/* saves space in the firmware */
 
@@ -40,11 +38,6 @@
 #define TPM_E_NEEDS_SELFTEST     ((u32)(TPM_E_NON_FATAL + 1))
 #define TPM_E_DOING_SELFTEST     ((u32)(TPM_E_NON_FATAL + 2))
 
-#if CONFIG_NO_TPM_RESUME
-static void init_vboot(int bootmode)
-{
-}
-#else
 static const struct {
 	u8 buffer[12];
 } tpm_resume_cmd = {
@@ -183,22 +176,21 @@
 	return result;
 }
 
-static void init_vboot(int bootmode)
+void init_tpm(int s3resume)
 {
 	u32 result;
 	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
 
-#ifdef UBOOT_DOES_TPM_STARTUP
 	/* Doing TPM startup when we're not coming in on the S3 resume path
 	 * saves us roughly 20ms in boot time only. This does not seem to
 	 * be worth an API change to vboot_reference-firmware right now, so
 	 * let's keep the code around, but just bail out early:
 	 */
-	if (bootmode != 2)
+	if (s3resume ? CONFIG_NO_TPM_RESUME
+	    : CONFIG_SKIP_TPM_STARTUP_ON_NORMAL_BOOT)
 		return;
-#endif
 
-	printk(BIOS_DEBUG, "Verified boot TPM initialization.\n");
+	printk(BIOS_DEBUG, "TPM initialization.\n");
 
 	printk(BIOS_SPEW, "TPM: Init\n");
 	if (tis_init())
@@ -209,7 +201,7 @@
 		return;
 
 
-	if (bootmode == 2) {
+	if (s3resume) {
 		/* S3 Resume */
 		printk(BIOS_SPEW, "TPM: Resume\n");
 		result = TlclSendReceive(tpm_resume_cmd.buffer,
@@ -232,17 +224,13 @@
 		return;
 	}
 
-#if !MOCK_TPM
-	printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result);
-	post_code(POST_TPM_FAILURE);
-	if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))
-		cbmem_dump_console();
-	hard_reset();
-#endif
-}
-#endif
+	printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result);
 
-void init_chromeos(int bootmode)
-{
-	init_vboot(bootmode);
+	if (CONFIG_TPM_INIT_FAILURE_IS_FATAL) {
+		printk(BIOS_ERR, "Hard reset!\n");
+		post_code(POST_TPM_FAILURE);
+		if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART))
+			cbmem_dump_console();
+		hard_reset();
+	}
 }
diff --git a/src/include/tpm.h b/src/include/tpm.h
index 464f32e..9b4db4a 100644
--- a/src/include/tpm.h
+++ b/src/include/tpm.h
@@ -66,4 +66,6 @@
 int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf,
 			size_t *recv_len);
 
+void init_tpm(int s3resume);
+
 #endif /* TPM_H_ */
diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig
index 2239f70..74e1edd 100644
--- a/src/mainboard/google/bolt/Kconfig
+++ b/src/mainboard/google/bolt/Kconfig
@@ -16,6 +16,7 @@
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig
index 7472c06..b1a64ee 100644
--- a/src/mainboard/google/butterfly/Kconfig
+++ b/src/mainboard/google/butterfly/Kconfig
@@ -13,6 +13,7 @@
 	select HAVE_CMOS_DEFAULT
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS
 
diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig
index a8faaab..5b97259 100644
--- a/src/mainboard/google/falco/Kconfig
+++ b/src/mainboard/google/falco/Kconfig
@@ -17,6 +17,7 @@
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select MAINBOARD_DO_NATIVE_VGA_INIT
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index 316434f..0f70925 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -12,6 +12,7 @@
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select SERIRQ_CONTINUOUS_MODE
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index ca8c2bd..b345d5e 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -41,9 +41,7 @@
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <tpm.h>
 #include <cbfs.h>
 
 #include <southbridge/intel/bd82x6x/chip.h>
@@ -246,8 +244,9 @@
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
-	init_chromeos(boot_mode);
-#endif
+	if (CONFIG_LPC_TPM) {
+		init_tpm(boot_mode == 2);
+	}
+
 	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig
index 31062ed..37a8548 100644
--- a/src/mainboard/google/panther/Kconfig
+++ b/src/mainboard/google/panther/Kconfig
@@ -15,6 +15,7 @@
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select INTEL_INT15
 	select PHYSICAL_REC_SWITCH
diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig
index 07405c6..9cf390a 100644
--- a/src/mainboard/google/parrot/Kconfig
+++ b/src/mainboard/google/parrot/Kconfig
@@ -12,6 +12,7 @@
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS
 
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index d0fab67..a947c48 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -39,10 +39,8 @@
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 #include <cbfs.h>
+#include <tpm.h>
 #include "ec/compal/ene932/ec.h"
 
 static void pch_enable_lpc(void)
@@ -197,8 +195,8 @@
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
-	init_chromeos(boot_mode);
-#endif
+	if (CONFIG_LPC_TPM) {
+		init_tpm(boot_mode == 2);
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig
index d6a208b..2c1560a 100644
--- a/src/mainboard/google/peppy/Kconfig
+++ b/src/mainboard/google/peppy/Kconfig
@@ -17,6 +17,7 @@
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select MAINBOARD_DO_NATIVE_VGA_INIT
diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index 4c9e891..1130d11 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -12,6 +12,7 @@
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select ALWAYS_LOAD_OPROM
 	select CHROMEOS_VBNV_CMOS
 
diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig
index f655b29..06317e9 100644
--- a/src/mainboard/google/samus/Kconfig
+++ b/src/mainboard/google/samus/Kconfig
@@ -15,6 +15,7 @@
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select CHROMEOS_RAMOOPS_DYNAMIC
 	select INTEL_INT15
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig
index fd4cb2f..cfbce5e 100644
--- a/src/mainboard/google/slippy/Kconfig
+++ b/src/mainboard/google/slippy/Kconfig
@@ -16,6 +16,7 @@
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select EXTERNAL_MRC_BLOB
 	select INTEL_DP
 	select INTEL_DDI
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
index ec03d87..eca83da 100644
--- a/src/mainboard/google/stout/Kconfig
+++ b/src/mainboard/google/stout/Kconfig
@@ -13,6 +13,7 @@
 	select HAVE_CMOS_DEFAULT
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS
 
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index ee6ca4f..31b61e2 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -40,9 +40,7 @@
 #include <halt.h>
 #include "gpio.h"
 #include <bootmode.h>
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
+#include <tpm.h>
 #include <cbfs.h>
 #include <ec/quanta/it8518/ec.h>
 #include "ec.h"
@@ -251,8 +249,8 @@
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
-	init_chromeos(boot_mode);
-#endif
+	if (CONFIG_LPC_TPM) {
+		init_tpm(boot_mode == 2);
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig
index c3e3361..f916138 100644
--- a/src/mainboard/intel/baskingridge/Kconfig
+++ b/src/mainboard/intel/baskingridge/Kconfig
@@ -11,6 +11,7 @@
 	select HAVE_ACPI_RESUME
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select INTEL_INT15
 	select CHROMEOS_VBNV_CMOS
 
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index c9d5cf1..bcf498b 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -39,10 +39,8 @@
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
+#include <tpm.h>
 #include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 
 #define SIO_PORT 0x164e
 
@@ -255,8 +253,8 @@
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
-	init_chromeos(boot_mode);
-#endif
+	if (CONFIG_LPC_TPM) {
+		init_tpm(boot_mode == 2);
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 5a064d1..b8f616a 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -9,6 +9,7 @@
 	select HAVE_ACPI_RESUME
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select INTEL_INT15
 
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
index 7c9dce4..fed4610 100644
--- a/src/mainboard/samsung/lumpy/Kconfig
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -5,6 +5,7 @@
 	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_8192
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select CPU_INTEL_SOCKET_RPGA989
 	select EC_SMSC_MEC1308
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 9b1a023..ce064bb 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -32,6 +32,7 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <bootmode.h>
+#include <tpm.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <southbridge/intel/bd82x6x/pch.h>
@@ -45,9 +46,6 @@
 #if CONFIG_DRIVERS_UART_8250IO
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 
 static void pch_enable_lpc(void)
 {
@@ -273,8 +271,8 @@
 	}
 	northbridge_romstage_finalize(boot_mode==2);
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
-	init_chromeos(boot_mode);
-#endif
+	if (CONFIG_LPC_TPM) {
+		init_tpm(boot_mode == 2);
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
index 1eda8eb..f749c39 100644
--- a/src/mainboard/samsung/stumpy/Kconfig
+++ b/src/mainboard/samsung/stumpy/Kconfig
@@ -4,6 +4,7 @@
 	def_bool y
 	select BOARD_ROMSIZE_KB_8192
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_LPC_TPM
 	select CPU_INTEL_SOCKET_RPGA989
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 6506c80..161c8d1 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -41,13 +41,11 @@
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
+#include <tpm.h>
 #include "gpio.h"
 #if CONFIG_DRIVERS_UART_8250IO
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 
 /* Stumpy USB Reset Disable defined in cmos.layout */
 #if CONFIG_USE_OPTION_TABLE
@@ -283,8 +281,8 @@
 	northbridge_romstage_finalize(boot_mode==2);
 
 	post_code(0x3f);
-#if CONFIG_CHROMEOS
-	init_chromeos(boot_mode);
-#endif
+	if (CONFIG_LPC_TPM) {
+		init_tpm(boot_mode == 2);
+	}
 	timestamp_add_now(TS_END_ROMSTAGE);
 }
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index bfc8678..a32db02 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -33,6 +33,7 @@
 #include <romstage_handoff.h>
 #include <stage_cache.h>
 #include <timestamp.h>
+#include <tpm.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
@@ -211,14 +212,6 @@
 	return prev_sleep_state;
 }
 
-static inline void chromeos_init(int prev_sleep_state)
-{
-#if CONFIG_CHROMEOS
-	/* Normalize the sleep state to what init_chromeos() wants for S3: 2. */
-	init_chromeos(prev_sleep_state == 3 ? 2 : 0);
-#endif
-}
-
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
@@ -250,7 +243,9 @@
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	chromeos_init(prev_sleep_state);
+	if (CONFIG_LPC_TPM) {
+		init_tpm(prev_sleep_state == 3);
+	}
 }
 
 void asmlinkage romstage_after_car(void)
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 9c8bbc4..5e5b8be 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -43,6 +43,7 @@
 #include <soc/romstage.h>
 #include <soc/smm.h>
 #include <soc/spi.h>
+#include <tpm.h>
 
 /* The cache-as-ram assembly file calls romstage_main() after setting up
  * cache-as-ram.  romstage_main() will then call the mainboards's
@@ -211,14 +212,6 @@
 	return prev_sleep_state;
 }
 
-static inline void chromeos_init(int prev_sleep_state)
-{
-#if CONFIG_CHROMEOS
-	/* Normalize the sleep state to what init_chromeos() wants for S3: 2. */
-	init_chromeos(prev_sleep_state == 3 ? 2 : 0);
-#endif
-}
-
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
@@ -250,7 +243,9 @@
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	chromeos_init(prev_sleep_state);
+	if (CONFIG_LPC_TPM) {
+		init_tpm(prev_sleep_state == 3);
+	}
 }
 
 void asmlinkage romstage_after_car(void)
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 50d5b24..e950b1e 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -29,6 +29,7 @@
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #include <elog.h>
+#include <tpm.h>
 #include <romstage_handoff.h>
 #include <stage_cache.h>
 #include <timestamp.h>
@@ -89,14 +90,6 @@
 	return setup_stack_and_mttrs();
 }
 
-static inline void chromeos_init(int prev_sleep_state)
-{
-#if CONFIG_CHROMEOS
-	/* Normalize the sleep state to what init_chromeos() wants for S3: 2 */
-	init_chromeos(prev_sleep_state == SLEEP_STATE_S3 ? 2 : 0);
-#endif
-}
-
 /* Entry from the mainboard. */
 void romstage_common(struct romstage_params *params)
 {
@@ -132,7 +125,9 @@
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
-	chromeos_init(params->power_state->prev_sleep_state);
+#if CONFIG_LPC_TPM
+	init_tpm(prev_sleep_state == SLEEP_STATE_S3);
+#endif
 }
 
 void asmlinkage romstage_after_car(void)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 4e7fdac..0b0b862 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -26,6 +26,8 @@
 	bool "Build for ChromeOS"
 	default n
 	select TPM
+	select TPM_INIT_FAILURE_IS_FATAL
+	select SKIP_TPM_STARTUP_ON_NORMAL_BOOT
 	select BOOTMODE_STRAPS
 	select ELOG
 	help
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index 67beaba..df24435 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -32,7 +32,6 @@
 romstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c
 ramstage-$(CONFIG_CHROMEOS_VBNV_FLASH) += vbnv_flash.c
 
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
 ramstage-$(CONFIG_ELOG) += elog.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c
 ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index e495a11..c7048dd 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -39,9 +39,6 @@
 void save_vbnv(const uint8_t *vbnv_copy);
 
 #if CONFIG_CHROMEOS
-/* functions implemented in vboot.c */
-void init_chromeos(int bootmode);
-
 /* functions implemented in elog.c */
 void elog_add_boot_reason(void);
 
@@ -53,7 +50,6 @@
 int vboot_enable_recovery(void);
 int vboot_skip_display_init(void);
 #else
-static inline void init_chromeos(int bootmode) { }
 static inline void elog_add_boot_reason(void) { return; }
 static inline void elog_add_watchdog_reset(void) { return; }
 static inline void reboot_from_watchdog(void) { return; }