nb/intel/sandybridge/gma.c: Remove useless if condition
There's a useless check with both branches doing the same: enabling RC6
and disabling RC6p. In past, this condition would enable RC6p in IVB but
not on SNB. Then, at some point, RC6p was considered unstable and was
disabled, but the condition remained.
It's not needed so let's remove it.
Change-Id: I926bb682d1b9d21185048224490b966c33204b6a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 83a0279..fee7513 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -453,18 +453,15 @@
gtt_write(0xa06c, 0x000493e0); /* RP Down EI */
gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
- /* 11a: Enable Render Standby (RC6) */
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
- /*
- * IvyBridge should also support DeepRenderStandby.
- *
- * Unfortunately it does not work reliably on all SKUs so
- * disable it here and it can be enabled by the kernel.
- */
- gtt_write(0xa090, 0x88040000); /* HW RC Control */
- } else {
- gtt_write(0xa090, 0x88040000); /* HW RC Control */
- }
+ /*
+ * 11a: Enable Render Standby (RC6)
+ *
+ * IvyBridge should also support DeepRenderStandby.
+ *
+ * Unfortunately it does not work reliably on all SKUs so
+ * disable it here and it can be enabled by the kernel.
+ */
+ gtt_write(0xa090, 0x88040000); /* HW RC Control */
/* 12: Normal Frequency Request */
/* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */