commit | 0de0254a1fef88a8758e0bdc81a25101cd3c9ccd | [log] [tgz] |
---|---|---|
author | Matt DeVillier <matt.devillier@gmail.com> | Sun Feb 13 13:43:35 2022 -0600 |
committer | Felix Held <felix-coreboot@felixheld.de> | Tue Feb 15 18:11:22 2022 +0000 |
tree | fd22c566434e716c60174650d8349adffeb2ea8a | |
parent | 575a2e589d50018946c6e7511cfc98610ea5bac8 [diff] |
soc/intel/cnl: Move selection of DISABLE_HECI1_AT_PRE_BOOT back to mainboard Commit 805956bce [soc/intel/cnl: Use Kconfig to disable HECI1] moved HECI1 disablement out of mainboard devicetree and into SoC Kconfig, but in doing so inadvertently disabled HECI1 for Puff-based boards which previously had HECI1 enabled by default. To correct this, move the Kconfig selection back into the mainboard Kconfig, and set defaults to match values prior to refactoring in 805956bce. Test: run menuconfig for boards google/{drallion,hatch,puff,sarien} and ensure Disable HECI1 option defaults to selected for all except Puff. Change-Id: Idf7001fb8b0dd94677cf2b5527a61b7a29679492 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.