commit 0d9b360b42d39d211d62f0c213aae9e7cf3f2924
author Ryan Salsamendi <rsalsamendi@hotmail.com> Fri Jun 30 17:15:57 2017 -0700
committer Martin Roth <martinroth@google.com> Sun Jul 02 18:54:39 2017 +0000
tree b4e0b236cdade276520d9d92b29fb3efe4c7b442
parent 0c731b512a6adf3aa9ecee5e89b6514e75ed6653

southbridge/intel/lynxpoint: Fix undefined behavior

Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.

Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/southbridge/intel/lynxpoint/pcie.c

diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 3fd8d1e..3d01cd6 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -608,7 +608,7 @@
 	pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11));
 	pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
 
-	pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
+	pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16));
 
 	/* Set L1 exit latency in LCAP register. */
 	if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))