tree f7091f1c391332e86cd2d9da9e84c40153d95c65
parent a891f71ad54898712e3f4228afcd05169cebb784
author Martin Roth <gaumless@gmail.com> 1672536442 -0700
committer Elyes Haouas <ehaouas@noos.fr> 1675767214 +0000

src: Move POST_BOOTBLOCK_CAR to common postcodes and use it

This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific
postcodes into the common postcode list, and uses it for the
cache-as-RAM init as needed.

Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in
most of the others, the values were consolidated into 0x21.  This will
change the value on some platforms.

Any conflicts should get sorted out later in the conversion process.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8527334e679a23006b77a5645f919aea76dd4926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>