soc/amd/picasso/romstage: factor out chipset state saving functionality
Since Cezanne needs the exact same code, move it to the common directory
and add a Kconfig option to add this functionality to the build.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/common/block/include/amdblocks/pmlib.h b/src/soc/amd/common/block/include/amdblocks/pmlib.h
index c778664..d9b80a2 100644
--- a/src/soc/amd/common/block/include/amdblocks/pmlib.h
+++ b/src/soc/amd/common/block/include/amdblocks/pmlib.h
@@ -17,4 +17,7 @@
*/
void pm_set_power_failure_state(void);
+/* stash ACPI PM/GPE and GPIO wake state before FSP-M call */
+void fill_chipset_state(void);
+
#endif /* SOC_AMD_COMMON_BLOCK_PMLIB_H */
diff --git a/src/soc/amd/common/block/pm/Kconfig b/src/soc/amd/common/block/pm/Kconfig
index c976d01..e250bf0 100644
--- a/src/soc/amd/common/block/pm/Kconfig
+++ b/src/soc/amd/common/block/pm/Kconfig
@@ -10,4 +10,10 @@
config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
default y
+config SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
+ bool
+ help
+ Add common functionality to write CBMEM_ID_POWER_STATE for AMD
+ platforms that use FSP for hardware initialization.
+
endif # SOC_AMD_COMMON_BLOCK_PM
diff --git a/src/soc/amd/common/block/pm/Makefile.inc b/src/soc/amd/common/block/pm/Makefile.inc
index f465e99..f016a9d 100644
--- a/src/soc/amd/common/block/pm/Makefile.inc
+++ b/src/soc/amd/common/block/pm/Makefile.inc
@@ -1 +1,3 @@
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c
+
+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c
diff --git a/src/soc/amd/common/block/pm/chipset_state.c b/src/soc/amd/common/block/pm/chipset_state.c
new file mode 100644
index 0000000..3a4a0ba
--- /dev/null
+++ b/src/soc/amd/common/block/pm/chipset_state.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpi.h>
+#include <amdblocks/gpio_banks.h>
+#include <amdblocks/pmlib.h>
+#include <cbmem.h>
+#include <string.h>
+
+static struct chipset_power_state chipset_state;
+
+void fill_chipset_state(void)
+{
+ acpi_fill_pm_gpe_state(&chipset_state.gpe_state);
+ gpio_fill_wake_state(&chipset_state.gpio_state);
+}
+
+static void add_chipset_state_cbmem(int unused)
+{
+ struct chipset_power_state *state;
+
+ state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
+
+ if (state)
+ memcpy(state, &chipset_state, sizeof(*state));
+}
+
+ROMSTAGE_CBMEM_INIT_HOOK(add_chipset_state_cbmem);
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 765ed60..b464539 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -40,6 +40,8 @@
select SOC_AMD_COMMON_BLOCK_LPC
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI
+ select SOC_AMD_COMMON_BLOCK_PM
+ select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
select SOC_AMD_COMMON_BLOCK_SATA
select SOC_AMD_COMMON_BLOCK_SMBUS
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 3e75ebe..7e20768 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -1,38 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
-#include <amdblocks/acpi.h>
#include <amdblocks/apob_cache.h>
#include <amdblocks/memmap.h>
+#include <amdblocks/pmlib.h>
#include <arch/cpu.h>
-#include <cbmem.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <fsp/api.h>
#include <program_loading.h>
-#include <soc/acpi.h>
#include <types.h>
-static struct chipset_power_state chipset_state;
-
-static void fill_chipset_state(void)
-{
- acpi_fill_pm_gpe_state(&chipset_state.gpe_state);
- gpio_fill_wake_state(&chipset_state.gpio_state);
-}
-
-static void add_chipset_state_cbmem(int unused)
-{
- struct chipset_power_state *state;
-
- state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
-
- if (state)
- memcpy(state, &chipset_state, sizeof(*state));
-}
-
-ROMSTAGE_CBMEM_INIT_HOOK(add_chipset_state_cbmem);
-
asmlinkage void car_stage_entry(void)
{
post_code(0x40);