include: Fix spelling
Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3755
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h
index 2f08fd8..baba6ce 100644
--- a/src/include/cpu/amd/amdfam10_sysconf.h
+++ b/src/include/cpu/amd/amdfam10_sysconf.h
@@ -64,7 +64,7 @@
unsigned lift_bsp_apicid;
int apicid_offset;
- void *mb; // pointer for mb releated struct
+ void *mb; // pointer for mb related struct
};
diff --git a/src/include/cpu/amd/amdk8_sysconf.h b/src/include/cpu/amd/amdk8_sysconf.h
index 3ae35fd..87bd4d5 100644
--- a/src/include/cpu/amd/amdk8_sysconf.h
+++ b/src/include/cpu/amd/amdk8_sysconf.h
@@ -19,7 +19,7 @@
unsigned lift_bsp_apicid;
int apicid_offset;
- void *mb; // pointer for mb releated struct
+ void *mb; // pointer for mb related struct
};
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index ee55c2f..beb4c65 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -399,12 +399,12 @@
#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
#define BMIO 6 /* Base Mask IO */
#define SCIO 7 /* Swiss 0xCeese IO */
-#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */
-#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */
-#define BMO_SMM 10 /* Specail marker for SMM */
-#define BM_SMM 11 /* Specail marker for SMM */
-#define BMO_DMM 12 /* Specail marker for DMM */
-#define BM_DMM 13 /* Specail marker for DMM */
+#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU */
+#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU */
+#define BMO_SMM 10 /* Special marker for SMM */
+#define BM_SMM 11 /* Special marker for SMM */
+#define BMO_DMM 12 /* Special marker for DMM */
+#define BM_DMM 13 /* Special marker for DMM */
#define RO_FB 14 /* special for Frame buffer. */
#define R_FB 15 /* special for FB. */
#define OTHER 0x0FE /* Special marker for other */
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 4eee156..da26895 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -533,12 +533,12 @@
#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
#define BMIO 6 /* Base Mask IO*/
#define SCIO 7 /* Swiss 0xCeese IO*/
-#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU*/
-#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU*/
-#define BMO_SMM 10 /* Specail marker for SMM*/
-#define BM_SMM 11 /* Specail marker for SMM*/
-#define BMO_DMM 12 /* Specail marker for DMM*/
-#define BM_DMM 13 /* Specail marker for DMM*/
+#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU*/
+#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU*/
+#define BMO_SMM 10 /* Special marker for SMM*/
+#define BM_SMM 11 /* Special marker for SMM*/
+#define BMO_DMM 12 /* Special marker for DMM*/
+#define BM_DMM 13 /* Special marker for DMM*/
#define RO_FB 14 /* special for Frame buffer.*/
#define R_FB 15 /* special for FB.*/
#define OTHER 0x0FE /* Special marker for other*/
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 38c3f7c..017a77e 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -47,14 +47,14 @@
* x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent
* of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers
* want to call the components of x86_setup_mtrrs() because of other
- * rquirements the ordering should still preserved.
+ * requirements the ordering should still preserved.
* 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because
* of the nature of the global MTRR enable flag. Therefore, all direct
* or indirect callers of enable_fixed_mtrr() should ensure that the
* variable MTRR MSRs do not contain bad ranges.
* 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling
* the caching of the ROM. However, it is set to uncacheable (UC). It
- * is the responsiblity of the caller to enable it by calling
+ * is the responsibility of the caller to enable it by calling
* x86_mtrr_enable_rom_caching().
*/
void x86_setup_mtrrs(void);
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index df7e3de..cacbff0 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -423,7 +423,7 @@
u32 save_state_size;
/* The apic_id_to_cpu provides a mapping from APIC id to cpu number.
* The cpu number is indicated by the index into the array by matching
- * the deafult APIC id and value at the index. The stub loader
+ * the default APIC id and value at the index. The stub loader
* initializes this array with a 1:1 mapping. If the APIC ids are not
* contiguous like the 1:1 mapping it is up to the caller of the stub
* loader to adjust this mapping. */
@@ -446,7 +446,7 @@
#else
/* SMM Module Loading API */
-/* Ths smm_loader_params structure provides direction to the SMM loader:
+/* The smm_loader_params structure provides direction to the SMM loader:
* - stack_top - optional external stack provided to loader. It must be at
* least per_cpu_stack_size * num_concurrent_stacks in size.
* - per_cpu_stack_size - stack size per cpu for smm modules.