mainboard/**/devicetree.cb: Fix typo
repalcement ---> replacement
Change-Id: I486170e89f75fa7c01c7322bb8db783fd4f61931
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64404
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 1349f69..2124dc4 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -183,7 +183,7 @@
# For an offset = 12.580, use 12580
register "ImonOffset" = "0"
- # Skip the CPU repalcement check
+ # Skip the CPU replacement check
register "SkipCpuReplacementCheck" = "1"
# Sagv Configuration
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
index baf0ba1..8b075ff 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
@@ -40,7 +40,7 @@
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3 WLAN
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # UNUSED
- # Skip the CPU repalcement check
+ # Skip the CPU replacement check
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 2120694..fdd1a78 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -53,7 +53,7 @@
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- # Skip the CPU repalcement check
+ # Skip the CPU replacement check
register "SkipCpuReplacementCheck" = "1"
register "PchHdaDspEnable" = "1"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 9bb8d8f..69277a5 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -38,7 +38,7 @@
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Port is not used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Port is not used
- # Skip the CPU repalcement check
+ # Skip the CPU replacement check
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 72e4f60..9883fd9 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -38,7 +38,7 @@
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # UNUSED
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # UNUSED
- # Skip the CPU repalcement check
+ # Skip the CPU replacement check
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs