tree 3b9cf3886eb4fda8a5301f729d24c3649f10ccc1
parent d560ad6e7a372c4e3d1c14d158ca9318c5b1ba90
author Curtis Chen <curtis.chen@intel.com> 1637293092 +0800
committer Felix Held <felix-coreboot@felixheld.de> 1637869380 +0000

soc/intel/alderlake: Add ADLP 4+4+2 power configurations

Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power
related settings.
Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for
ADL-P 482(28W) and 442(45W).

BUG=b:193864533
TEST=Build and check fsp log to confirm the settings are set properly.

Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>