tree d56d5916781b64e7045cc350283973cff5c73136
parent df4fa45ce4fe59ddd339e7837fefa504fb34cc40
author Nico Huber <nico.h@gmx.de> 1565524590 +0200
committer Felix Held <felix-coreboot@felixheld.de> 1674739721 +0000

nb/intel/gm45: Wedge DDR2 SPD support in

Add initial support for DDR2. This also changes GM45 raminit to
internally work in units of 1/256 ns for both DDR2 and DDR3 instead of
the 1/8 ns MTB assumed for DDR3, which simplifies the handling of time
values. DDR3 time values are thus scaled by a factor of 32 accordingly.

TODO:
- DDR2 JEDEC init
- Memory IO init
- Register programming

TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200

Change-Id: I265938d58c30264fd5d4f7b89da7b689058b8cf8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>