ACPI: Drop typedef global_nvs_t
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 595e6a2..1c7a04a 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <console/console.h>
#include <device/mmio.h>
@@ -70,7 +71,7 @@
return cstate_map;
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
struct soc_intel_apollolake_config *cfg;
cfg = config_of_soc();
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index f9af4f4..dd7dd1a 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -320,7 +320,7 @@
p2sb_unhide();
/* Allocate ACPI NVS in CBMEM */
- cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t));
+ cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 4668e1a..45301c4 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * NOTE: The layout of the global_nvs_t structure below must match the layout
+ * NOTE: The layout of the global_nvs structure below must match the layout
* in soc/intel/apollolake/acpi/globalnvs.asl !!!
*
*/
@@ -12,7 +12,7 @@
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
uint8_t pcnt; /* 0x00 - Processor Count */
uint8_t ppcm; /* 0x01 - Max PPC State */
@@ -38,7 +38,8 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
+
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 13acf86..9bcd786 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -57,7 +58,7 @@
}
};
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* Set unknown wake source */
gnvs->pm1i = -1;
diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h
index fc8f8ab..98b8283 100644
--- a/src/soc/intel/baytrail/include/soc/acpi.h
+++ b/src/soc/intel/baytrail/include/soc/acpi.h
@@ -7,6 +7,5 @@
#include <soc/nvs.h>
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
#endif /* _BAYTRAIL_ACPI_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index cc70f78..cdffc75 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -7,7 +7,7 @@
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/device_nvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -53,12 +53,8 @@
/* Baytrail LPSS (0x1000) */
device_nvs_t dev;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-void acpi_create_gnvs(global_nvs_t *gnvs);
-
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _BAYTRAIL_NVS_H_ */
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 78638de..3a12a4b 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -50,7 +50,7 @@
LPE_PCICFGCTR1_ACPI_INT_EN),
REG_SCRIPT_END
};
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index d5c3e4d..cdf78b7 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -28,7 +28,7 @@
REG_SCRIPT_END
};
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index d27a17d..995fe20 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -117,7 +117,7 @@
}
/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
-static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
+static void s3_save_acpi_wake_source(struct global_nvs *gnvs)
{
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
uint16_t pm1;
@@ -144,14 +144,14 @@
static void s3_resume_prepare(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (gnvs == NULL)
return;
if (!acpi_is_wakeup_s3())
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
else
s3_save_acpi_wake_source(gnvs);
}
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index 455f243..f178e83 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -81,7 +81,7 @@
REG_SCRIPT_END
};
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 91eb6f5..2a56f84 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -19,7 +19,7 @@
#include <soc/nvs.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
-static global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
static int smm_initialized;
int southbridge_io_trap_handler(int smif)
@@ -44,7 +44,7 @@
enable_smi(EOS);
}
-global_nvs_t *smm_get_gnvs(void)
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -330,7 +330,7 @@
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((uint32_t)state->rbx);
+ gnvs = (struct global_nvs *)((uint32_t)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 679c04d..38f51ff 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -5,6 +5,7 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
@@ -482,7 +483,7 @@
static void southcluster_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 1290d62..98d7980 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -61,7 +62,7 @@
}
};
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* Set unknown wake source */
gnvs->pm1i = -1;
@@ -493,7 +494,7 @@
void southcluster_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index 5bff07a..cd54f2c 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -8,7 +8,6 @@
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
void southcluster_inject_dsdt(const struct device *device);
unsigned long southcluster_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 22ea10f..35ab47a 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -7,7 +7,7 @@
#include <soc/device_nvs.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -55,11 +55,8 @@
/* LPSS (0x1000) */
device_nvs_t dev;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-void acpi_create_gnvs(global_nvs_t *gnvs);
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index f3391de..0fb4ca9 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -53,7 +53,7 @@
REG_SCRIPT_END
};
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index 8200248..d9027f5 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -27,7 +27,7 @@
REG_SCRIPT_END
};
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 893a6b6..eba1527 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -137,16 +137,16 @@
static void s3_resume_prepare(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (!acpi_is_wakeup_s3() && gnvs)
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
}
static void set_board_id(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index 0b6385f..6f23fda 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -12,7 +12,7 @@
void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n",
__FILE__, __func__, dev_name(dev), iosf_reg, nvs_index);
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index 614f56d..28765d0 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -19,7 +19,7 @@
#include <smmstore.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
-static global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
static int smm_initialized;
int southbridge_io_trap_handler(int smif)
@@ -45,7 +45,7 @@
enable_smi(EOS);
}
-global_nvs_t *smm_get_gnvs(void)
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -307,7 +307,7 @@
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((uint32_t)state->rbx);
+ gnvs = (struct global_nvs *)((uint32_t)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 43ff8eb..306d72f 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <cbmem.h>
@@ -148,7 +149,7 @@
return cores;
}
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* Set unknown wake source */
gnvs->pm1i = -1;
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 897f9c4..15858e1 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -80,7 +80,7 @@
if (config->sio_acpi_mode) {
/* Configure for ACPI mode */
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n");
diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h
index 46cc42a..0bf63a4 100644
--- a/src/soc/intel/broadwell/include/soc/acpi.h
+++ b/src/soc/intel/broadwell/include/soc/acpi.h
@@ -13,7 +13,6 @@
#define PSS_LATENCY_BUSMASTER 10
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
unsigned long northbridge_write_acpi_tables(const struct device *dev,
unsigned long current, struct acpi_rsdp *rsdp);
#endif
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 8772a02..afeed6f 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -7,7 +7,7 @@
#include <soc/device_nvs.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -45,12 +45,8 @@
/* Device specific (0x1000) */
device_nvs_t dev;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-void acpi_create_gnvs(global_nvs_t *gnvs);
-
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 1e96286..58cd35d 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -11,6 +11,7 @@
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
#include <reg_script.h>
@@ -553,7 +554,7 @@
static void pch_lpc_read_resources(struct device *dev)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -565,14 +566,14 @@
pch_lpc_add_io_resources(dev);
/* Allocate ACPI NVS in CBMEM */
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (!acpi_is_wakeup_s3() && gnvs)
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
}
static void southcluster_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index 39550b7..c414d62 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -32,14 +32,14 @@
static void s3_resume_prepare(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (gnvs == NULL)
return;
if (!acpi_is_wakeup_s3())
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
}
void broadwell_init_pre_device(void *chip_info)
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 4da3979..dbe194a 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -233,7 +233,7 @@
}
if (config->sio_acpi_mode) {
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 85d6ae0..c7cefdc 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -29,8 +29,8 @@
* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-static global_nvs_t *gnvs;
-global_nvs_t *smm_get_gnvs(void)
+static struct global_nvs *gnvs;
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -350,7 +350,7 @@
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((u32)state->rbx);
+ gnvs = (struct global_nvs *)((u32)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index c041eb0..1f3fbec 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <cbmem.h>
@@ -182,7 +183,7 @@
return read32((void *)pmc_bar + IRQ_REG);
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
const struct soc_intel_cannonlake_config *config;
config = config_of_soc();
diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c
index 1342c80..f30ef9f 100644
--- a/src/soc/intel/common/acpi_wake_source.c
+++ b/src/soc/intel/common/acpi_wake_source.c
@@ -16,7 +16,7 @@
/* Save wake source data for ACPI _SWS methods in NVS */
static void acpi_save_wake_source(void *unused)
{
- global_nvs_t *gnvs = acpi_get_gnvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
uint32_t pm1, *gpe0;
int gpe_reg, gpe_reg_count;
int reg_size = sizeof(uint32_t) * 8;
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 3265131..5e4c6e8 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -222,13 +222,13 @@
}
#endif
-__weak void acpi_create_gnvs(struct global_nvs_t *gnvs)
+__weak void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
void southbridge_inject_dsdt(const struct device *device)
{
- struct global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
@@ -457,7 +457,7 @@
/* Save wake source data for ACPI _SWS methods in NVS */
static void acpi_save_wake_source(void *unused)
{
- global_nvs_t *gnvs = acpi_get_gnvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
uint32_t pm1, *gpe0;
int gpe_reg, gpe_reg_count;
int reg_size = sizeof(uint32_t) * 8;
diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h
index 19dd68a..21664c8 100644
--- a/src/soc/intel/common/block/include/intelblocks/acpi.h
+++ b/src/soc/intel/common/block/include/intelblocks/acpi.h
@@ -12,7 +12,7 @@
struct chipset_power_state;
/* Forward declare the global nvs structure here */
-struct global_nvs_t;
+struct global_nvs;
/* Return ACPI name for this device */
const char *soc_acpi_name(const struct device *dev);
@@ -32,19 +32,6 @@
struct acpi_rsdp *rsdp);
/*
- * Creates acpi gnvs and adds it to the DSDT table.
- * GNVS creation is chipset specific and is done in soc specific acpi.c file.
- */
-void southbridge_inject_dsdt(const struct device *device);
-
-/*
- * This function populates the gnvs structure in acpi table.
- * Defined as weak in common acpi as gnvs structure definition is
- * chipset specific.
- */
-void acpi_create_gnvs(struct global_nvs_t *gnvs);
-
-/*
* get_cstate_map returns a table of processor specific acpi_cstate_t entries
* and number of entries in the table
*/
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index e1040ea..cc240c5 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -6,7 +6,7 @@
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - 0x01 Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -31,7 +31,8 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
+
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h
index e6c9905..56e4a16 100644
--- a/src/soc/intel/common/block/include/intelblocks/sgx.h
+++ b/src/soc/intel/common/block/include/intelblocks/sgx.h
@@ -18,6 +18,6 @@
void sgx_configure(void *unused);
/* Fill GNVS data with SGX status, EPC base and length */
-void sgx_fill_gnvs(global_nvs_t *gnvs);
+void sgx_fill_gnvs(struct global_nvs *gnvs);
#endif /* SOC_INTEL_COMMON_BLOCK_SGX_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index 428a9f3..7cea1dd 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -7,7 +7,7 @@
#include <stdint.h>
struct gpi_status;
-struct global_nvs_t;
+struct global_nvs;
/*
* The register value is used with get_reg and set_reg
@@ -127,11 +127,6 @@
void smihandler_southbridge_espi(
const struct smm_save_state_ops *save_state_ops);
-/*
- * Returns gnvs pointer within SMM context
- */
-struct global_nvs_t *smm_get_gnvs(void);
-
/* SoC overrides. */
/* Specific SOC SMI handler during ramstage finalize phase */
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index ae72116..cf56138 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -71,7 +71,7 @@
/* API to get TSEG size */
size_t sa_get_tseg_size(void);
/* Fill MMIO resource above 4GB into GNVS */
-void sa_fill_gnvs(global_nvs_t *gnvs);
+void sa_fill_gnvs(struct global_nvs *gnvs);
/*
* SoC overrides
*
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 9fe48d1f..ea85911 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index 56648c8..8679f1f 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -235,7 +235,7 @@
activate_sgx();
}
-void sgx_fill_gnvs(global_nvs_t *gnvs)
+void sgx_fill_gnvs(struct global_nvs *gnvs)
{
struct cpuid_result cpuid_regs;
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index ab5e9c2..73dfda5 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -27,7 +27,7 @@
#include <stdint.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
-static struct global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
/* SoC overrides. */
@@ -125,7 +125,7 @@
pmc_enable_smi(EOS);
}
-struct global_nvs_t *smm_get_gnvs(void)
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -380,7 +380,7 @@
if (state) {
/* EBX in the state save contains the GNVS pointer */
uint32_t reg_ebx = save_state_ops->get_reg(state, RBX);
- gnvs = (struct global_nvs_t *)(uintptr_t)reg_ebx;
+ gnvs = (struct global_nvs *)(uintptr_t)reg_ebx;
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c
index 1e9f4d9..1d6fb81 100644
--- a/src/soc/intel/common/block/smm/smitraphandler.c
+++ b/src/soc/intel/common/block/smm/smitraphandler.c
@@ -24,7 +24,7 @@
/* Inherited from cpu/x86/smm.h resulting in a different signature */
int southbridge_io_trap_handler(int smif)
{
- global_nvs_t *gnvs = smm_get_gnvs();
+ struct global_nvs *gnvs = smm_get_gnvs();
switch (smif) {
case 0x32:
printk(BIOS_DEBUG, "OS Init\n");
@@ -61,7 +61,7 @@
u32 data, mask = 0;
u8 trap_sts;
int i;
- global_nvs_t *gnvs = smm_get_gnvs();
+ struct global_nvs *gnvs = smm_get_gnvs();
/* TRSR - Trap Status Register */
trap_sts = pcr_read8(PID_PSTH, PCR_PSTH_TRPST);
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index d25e1aa..e6bbfc7 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -103,7 +103,7 @@
}
/* Fill MMIO resource above 4GB into GNVS */
-void sa_fill_gnvs(global_nvs_t *gnvs)
+void sa_fill_gnvs(struct global_nvs *gnvs)
{
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 0c641f3..fac0577 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -167,7 +167,7 @@
*/
static bool pch_uart_init_debug_controller_on_resume(void)
{
- global_nvs_t *gnvs = acpi_get_gnvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs)
return !!gnvs->uior;
diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c
index 099be5d..39baf01 100644
--- a/src/soc/intel/common/nhlt.c
+++ b/src/soc/intel/common/nhlt.c
@@ -13,7 +13,7 @@
uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id,
uint32_t oem_revision)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index 3f416b6..92a9c2a 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <cpu/x86/smm.h>
@@ -57,7 +58,7 @@
}
};
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
@@ -280,7 +281,7 @@
void southcluster_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h
index 00700a6..9bc5ed0 100644
--- a/src/soc/intel/denverton_ns/include/soc/acpi.h
+++ b/src/soc/intel/denverton_ns/include/soc/acpi.h
@@ -8,7 +8,6 @@
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
unsigned long southcluster_write_acpi_tables(const struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp);
diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h
index 0195643..4aaabc9 100644
--- a/src/soc/intel/denverton_ns/include/soc/nvs.h
+++ b/src/soc/intel/denverton_ns/include/soc/nvs.h
@@ -3,7 +3,7 @@
#ifndef _DENVERTON_NS_NVS_H_
#define _DENVERTON_NS_NVS_H_
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -47,9 +47,6 @@
u32 tsegl; /* 0x58 - TSEG Length/Size */
u8 rsvd3[164];
-} __packed global_nvs_t;
-
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+};
#endif /* _DENVERTON_NS_NVS_H_ */
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index b81eb11..aa87630 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -17,7 +17,7 @@
#include <soc/nvs.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
-static global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
static int smm_initialized;
int southbridge_io_trap_handler(int smif)
@@ -39,7 +39,7 @@
void southbridge_smi_set_eos(void) { enable_smi(EOS); }
-global_nvs_t *smm_get_gnvs(void) { return gnvs; }
+struct global_nvs *smm_get_gnvs(void) { return gnvs; }
static void busmaster_disable_on_bus(int bus)
{
@@ -241,7 +241,7 @@
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((uint32_t)state->rbx);
+ gnvs = (struct global_nvs *)((uint32_t)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index 796e770..ece28cc 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -178,7 +179,7 @@
return read32((void *)pmc_bar + IRQ_REG);
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
config_t *config = config_of_soc();
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
index 88ec5fe..9d5080b 100644
--- a/src/soc/intel/jasperlake/acpi.c
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -272,7 +273,7 @@
return current;
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
config_t *config = config_of_soc();
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 6fde1e2..6da43e9 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/cpu.h>
#include <arch/ioapic.h>
@@ -155,7 +156,7 @@
return cores;
}
-static void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
const struct soc_intel_skylake_config *config = config_of_soc();
@@ -643,7 +644,7 @@
void southbridge_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h
index 3422ece..bf81afb 100644
--- a/src/soc/intel/skylake/include/soc/acpi.h
+++ b/src/soc/intel/skylake/include/soc/acpi.h
@@ -13,7 +13,6 @@
#define PSS_LATENCY_BUSMASTER 10
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void southbridge_inject_dsdt(const struct device *device);
unsigned long southbridge_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
unsigned long northbridge_write_acpi_tables(const struct device *,
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 4973597..87f16fb 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -6,7 +6,7 @@
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -51,7 +51,8 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
+
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 0991134..4b31c6d 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -272,7 +273,7 @@
return current;
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
config_t *config = config_of_soc();
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c
index e52d75d..c554977 100644
--- a/src/soc/intel/xeon_sp/cpx/acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/acpi.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
@@ -108,7 +109,7 @@
void southbridge_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
@@ -133,7 +134,7 @@
uncore_inject_dsdt();
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h
index 08ad0f7..becdd76 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h
@@ -8,10 +8,10 @@
/* TODO - this requires xeon sp, server board support */
/* NOTE: We do not use intelblocks/nvs.h since it includes
mostly client specific attributes */
-typedef struct global_nvs_t {
+struct __packed global_nvs {
uint8_t pcnt; /* 0x00 - Processor Count */
uint32_t cbmc; /* 0x01 - coreboot memconsole */
uint8_t rsvd3[251];
-} __packed global_nvs_t;
+};
#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c
index 606bfed..903fc73 100644
--- a/src/soc/intel/xeon_sp/skx/acpi.c
+++ b/src/soc/intel/xeon_sp/skx/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <assert.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <intelblocks/acpi.h>
@@ -47,7 +48,7 @@
return sci_irq;
}
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
@@ -956,7 +957,7 @@
void southbridge_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h
index c1d61c9..0e00c2b 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h
@@ -14,7 +14,6 @@
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
unsigned long northbridge_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
void uncore_inject_dsdt(void);
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h
index 08ad0f7..becdd76 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h
@@ -8,10 +8,10 @@
/* TODO - this requires xeon sp, server board support */
/* NOTE: We do not use intelblocks/nvs.h since it includes
mostly client specific attributes */
-typedef struct global_nvs_t {
+struct __packed global_nvs {
uint8_t pcnt; /* 0x00 - Processor Count */
uint32_t cbmc; /* 0x01 - coreboot memconsole */
uint8_t rsvd3[251];
-} __packed global_nvs_t;
+};
#endif /* _SOC_NVS_H_ */